Xilinx ML605 AA3 PCIERX7P, AA4 PCIERX7N, PCIE100MMGT0P, GTXE1X0Y6, PCIE100MMGT0N, NQ0, GTXE1X0Y4

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Chapter 1: ML605 Evaluation Board

Table 1-8:PCIe Edge Connector Connections (Cont’d)

U1 FPGA

Schematic Net Name

P1 PCIe Edge Connector

Description

Package

 

 

Pin

Pin Number

Pin Name

Placement

 

 

 

 

 

 

 

 

 

 

 

 

AA3

PCIE_RX7_P

B45

PETp7

Integrated Endpoint block

GTXE1_X0Y7

 

 

 

 

AA4

PCIE_RX7_N

B46

PETn7

receive pair

 

 

 

 

 

 

 

 

 

P6

PCIE_100M_MGT0_P

U14.16

Q0

Sourced from U14 ICS854104

GTXE1_X0Y6

 

 

 

 

 

P5

PCIE_100M_MGT0_N

U14.15

NQ0

clock driver

 

 

 

 

 

 

 

V6

PCIE_250M_MGT1_P

U9.18

Q

Sourced from U9 ICS874001

GTXE1_X0Y4

 

 

 

 

 

V5

PCIE_250M_MGT1_N

U9.17

NQ

clock multiplier/driver

 

 

 

 

 

 

 

U14.6

PCIE_CLK_QO_P

A13

REFCLK+

Integrated Endpoint block

 

 

 

 

 

differential clock pair from PCIe

 

U14.7

PCIE_CLK_QO_N

A14

REFCLK-

 

edge connector

 

 

 

 

 

 

 

J42.2,4,6

PCIE_PRSNT_B

A1

PRSNT#1

J42 Lane Size Select jumper

 

 

 

 

 

 

 

 

 

 

 

Integrated Endpoint block wake

 

AD22

PCIE_WAKE_B

B11

WAKE#

signal, not connected on ML605

 

 

 

 

 

board

 

 

 

 

 

 

 

AE13

PCIE_PERST_B

A11

PERST

Integrated Endpoint block reset

 

signal

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

1.PCIE_TXn_P/N pairs are capacitively coupled to FPGA

2.PCIE_100M_MGT0_P/N pairs are capacitively coupled to FPGA

3.PCIE_250M_MGT1_P/N pairs are capacitively coupled to FPGA

4.PCIE_PERST_B is level-shifted by U32

5.For ML605, access is through MGT Banks 114 and 115

The PCIe interface obtains its power from the DC power supply provided with the ML605 or through the 12V ATX power supply connector. The PCIe edge connector is not used for any power connections.

The board can be powered by one of two 12V sources; J60, a 6-pin (2x3) molex-type connector and J25, a 4-pin (inline) ATX disk drive type connector.

The 6-pin molex-type connector provides 60W (12V @ 5A) from the AC power adapter provided with the board while the 4-pin ATX disk drive connector is provided for users who want to power their board while it is installed inside a PC chassis.

For applications requiring additional power, such as the use of expansion cards drawing significant power, a larger AC adapter might be required. If a different AC adapter is used, its load regulation should be better than ±10%.

ML605 power switch SW2 turns the board on and off by controlling the 12V supply to the board.

Caution! Never apply power to the power brick connector (J60) and the 4-pin ATX disk drive connector (J25) at the same time as this will result in damage to the board. See Figure 1-23, page 53. Never connect an auxiliary PCIe 6-pin molex power connector to J60 6-pin molex on the ML605 board as this could result in damage to the PCIe motherboard and/or ML605 board. The 6-pin molex connector is marked with a no PCIe power label to warn users of the potential hazard.

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ML605 Hardware User Guide

 

 

UG534 (v1.2.1) January 21, 2010

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Contents ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optionalRevision History Date Version RevisionTable of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This GuideML605 Evaluation Board Additional InformationSMA FeaturesML605 Evaluation Board IIC Eeprom 1 KBOverview Fpga Init Fpga DoneBlock Diagram 1ML605 High-Level Block DiagramDetailed Description ML605 FeaturesFeature DDR3 SodimmSgmii ML605 Evaluation Board ML605 Features Cont’dWDW6TP Configuration Virtex-6 XC6VLX240T-1FFG1156 FpgaCclk Direction 2Virtex-6 Fpga Configuration Modes M20Voltage Rails 3Voltage Rails U1 Fpga BankVCC1V5FPGA MB DDR3 Memory SodimmDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank 4DDR3 Sodimm ConnectionsML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI FlashML605 Flash Boot Options FLASHD2 DQ2 FLASHD0 DQ0FLASHD1 DQ1 FLASHD3 DQ3Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Differential Clock GenerationOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location IdentifiersSmarefclkn SMA PinSmarefclkp Multi-Gigabit Transceivers GTX MGTs ICSPCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J428PCIe Edge Connector Connections PCIE100MMGT0P AA3 PCIERX7PAA4 PCIERX7N GTXE1X0Y6SFP Module Connector 11 /100/1000 Tri-Speed Ethernet PHY 11PHY Default Interface Mode Jumper Settings J66 J67 J6812Board Connections for PHY Configuration Pins Bit2 Bit1 Bit013Ethernet PHYConnections U1 Fpga Pin 12Board Connections for PHY Configuration Pins Cont’dSgmii GTX Transceiver Clock Generation U80 M88E1111PHYRXD5 PHYRXD4RXD4 RXD5Vbus USB-to-UART BridgeGround 16USB Controller Connections USB ControllerU81 USB Controller 17DVI Controller Connections DVI CodecU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Iicsdamain SDA Kb NV MemoryIicsclmain SCL Designator Signal Name Color Label Description Status LEDsEthernet PHY Status LEDs 16Ethernet PHY Status LEDsControlled LED User I/OFpga Init and Done LEDs Fpgainitb18User LEDs and Gpio Connector, Directional LEDs User LEDsDetailed Description 21User LED Connections Fpga U1 Pin User Pushbutton SwitchesGpio J62 Pin Controlled LED User DIP Switch Switch PinUsersmagpion User SMA GpioUsersmagpiop LCD Display 16 Character x 2 Lines J41 PinSwitches Power On/Off Slide Switch SW2Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-LowSystem ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S126ML605 Configuration Modes M20 Bus WidthVita 57.1 FMC HPC Connector Master BPI28VITA 57.1 FMC HPC Connections HPC Pin28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB13P FMCHPCHB09NFMCHPCHB08P FMCHPCHB08NDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d VREFAM2C Vadj VadjVIOBM2C Vadj VREFBM2CVita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC PinAC Adapter and Input Power Jack/Switch Power ManagementDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d Onboard Power Regulation 28ML605 Onboard Power RegulatorsVccaux UCD9240PFCVccintfpga UCD7230RGWRSystem Monitor 29System Monitor External ReferenceSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Table A-1Default Switch Settings Function/Type DefaultGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References
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