Xilinx ML605 manual NET Iicsdadvi

Page 87

NET "FPGA_M0"

NET "FPGA_M1"

NET "FPGA_M2"

NET "FPGA_PROG_B" NET "FPGA_TCK" NET "FPGA_TDI" NET "FPGA_TMS" NET "FPGA_VBATT"

##

NET "GPIO_DIP_SW1" NET "GPIO_DIP_SW2" NET "GPIO_DIP_SW3" NET "GPIO_DIP_SW4" NET "GPIO_DIP_SW5" NET "GPIO_DIP_SW6" NET "GPIO_DIP_SW7" NET "GPIO_DIP_SW8"

##

NET "GPIO_LED_0"

NET "GPIO_LED_1"

NET "GPIO_LED_2"

NET "GPIO_LED_3"

NET "GPIO_LED_4"

NET "GPIO_LED_5"

NET "GPIO_LED_6"

NET "GPIO_LED_7"

##

NET "GPIO_LED_C"

NET "GPIO_LED_E"

NET "GPIO_LED_N"

NET "GPIO_LED_S"

NET "GPIO_LED_W"

##

NET "GPIO_SW_C"

NET "GPIO_SW_E"

NET "GPIO_SW_N"

NET "GPIO_SW_S"

NET "GPIO_SW_W"

##

NET "IIC_SCL_DVI"

NET "IIC_SCL_MAIN_LS" NET "IIC_SCL_SFP"

NET "IIC_SDA_DVI"

NET "IIC_SDA_MAIN_LS" NET "IIC_SDA_SFP"

##

NET "LCD_DB4_LS"

NET "LCD_DB5_LS"

NET "LCD_DB6_LS"

NET "LCD_DB7_LS" NET "LCD_E_LS" NET "LCD_RS_LS" NET "LCD_RW_LS"

##

NET "P30_CS_SEL"

##

NET "PCIE_100M_MGT0_N" NET "PCIE_100M_MGT0_P" NET "PCIE_250M_MGT1_N" NET "PCIE_250M_MGT1_P" NET "PCIE_PERST_B_LS"

NET "PCIE_RX0_N"

NET "PCIE_RX0_P"

NET "PCIE_RX1_N"

NET "PCIE_RX1_P"

LOC = "U8"; LOC = "W8"; LOC = "V8"; LOC = "L8"; LOC = "AE8"; LOC = "AD8"; LOC = "AF8"; LOC = "N8";

LOC = "D22"; LOC = "C22"; LOC = "L21"; LOC = "L20"; LOC = "C18"; LOC = "B18"; LOC = "K22"; LOC = "K21";

LOC = "AC22"; LOC = "AC24"; LOC = "AE22"; LOC = "AE23"; LOC = "AB23"; LOC = "AG23"; LOC = "AE24"; LOC = "AD24";

LOC = "AP24"; LOC = "AE21"; LOC = "AH27"; LOC = "AH28"; LOC = "AD21";

LOC = "G26"; LOC = "G17"; LOC = "A19"; LOC = "A18"; LOC = "H17";

LOC = "AN10"; LOC = "AK9"; LOC = "AA34"; LOC = "AP10"; LOC = "AE9"; LOC = "AA33";

LOC = "AD14"; LOC = "AK11"; LOC = "AJ11"; LOC = "AE12"; LOC = "AK12"; LOC = "T28"; LOC = "AC14";

LOC = "AJ12";

LOC = "P5"; LOC = "P6"; LOC = "V5"; LOC = "V6"; LOC = "AE13"; LOC = "J4"; LOC = "J3"; LOC = "K6"; LOC = "K5";

## 3

on

S2

DIP switch (active-High)

##

4

on

S2

DIP

switch

(active-High)

##

4

on

S2

DIP

switch

(active-High)

##1 on SW4 pushbutton (active-Low)

##80 on U19

##82 on U19

##85 on U19

##1 on B1 (battery + terminal)

##1 on SW1 DIP switch (active-High)

##2 on SW1 DIP switch (active-High)

##3 on SW1 DIP switch (active-High)

##4 on SW1 DIP switch (active-High)

##5 on SW1 DIP switch (active-High)

##6 on SW1 DIP switch (active-High)

##7 on SW1 DIP switch (active-High)

##8 on SW1 DIP switch (active-High)

##2 on LED DS12, 1 on J62

##2 on LED DS11, 2 on J62

## 2 on LED DS9, 3 on J62

##2 on LED DS10, 4 on J62

##2 on LED DS15, 5 on J62

##2 on LED DS14, 6 on J62

##2 on LED DS22, 7 on J62

##2 on LED DS21, 8 on J62

##2 on LED DS16

##2 on LED DS19

##2 on LED DS20

##2 on LED DS18

##2 on LED DS17

##2 on SW9 pushbutton (active-High)

##2 on SW7 pushbutton (active-High)

##2 on SW5 pushbutton (active-High)

##2 on SW6 pushbutton (active-High)

##2 on SW8 pushbutton (active-High)

##2 on Q5, 15 on U38

##2 on Q19

##2 on Q23

##2 on Q6, 14 on U38

##2 on Q20

##2 on Q21

##4 on J41

##3 on J41

##2 on J41

##1 on J41

##9 on J41

##11 on J41

##10 on J41

##2 on S2 DIP switch (active-High),1 on U10

##15 on U14

##16 on U14

##18 on U9

##17 on U9

##4 on U32

##B15 on P1

##B14 on P1

##B20 on P1

##B19 on P1

ML605 Hardware User Guide

www.xilinx.com

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UG534 (v1.2.1) January 21, 2010

 

 

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Page 86 Page 88
Contents UG534 v1.2.1 January 21, 2010 optional ML605 Hardware User GuideDate Version Revision Revision HistoryTable of Contents ML605 Hardware User Guide About This Guide Preface About This Guide Additional Support ResourcesAdditional Information ML605 Evaluation BoardIIC Eeprom 1 KB FeaturesML605 Evaluation Board SMAFpga Init Fpga Done Overview1ML605 High-Level Block Diagram Block DiagramDDR3 Sodimm ML605 FeaturesFeature Detailed DescriptionML605 Evaluation Board ML605 Features Cont’d SgmiiWDW6TP Virtex-6 XC6VLX240T-1FFG1156 Fpga Configuration3Voltage Rails U1 Fpga Bank 2Virtex-6 Fpga Configuration Modes M20Voltage Rails Cclk Direction4DDR3 Sodimm Connections MB DDR3 Memory SodimmDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank VCC1V5FPGADDR3A9 ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’dDDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref MB Linear BPI Flash Mb Platform Flash XLML605 Flash Boot Options FLASHD3 DQ3 FLASHD0 DQ0FLASHD1 DQ1 FLASHD2 DQ2Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Clock Generation Oscillator DifferentialOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers 8ML605 Oscillator Pin 1 Location Identifiers SMA Connectors DifferentialSMA Pin SmarefclknSmarefclkp ICS Multi-Gigabit Transceivers GTX MGTs12PCIe Lane Size Select Jumper J42 PCI Express Endpoint Connectivity8PCIe Edge Connector Connections GTXE1X0Y6 AA3 PCIERX7PAA4 PCIERX7N PCIE100MMGT0PSFP Module Connector Bit2 Bit1 Bit0 11PHY Default Interface Mode Jumper Settings J66 J67 J6812Board Connections for PHY Configuration Pins 11 /100/1000 Tri-Speed Ethernet PHYU80 M88E1111 12Board Connections for PHY Configuration Pins Cont’dSgmii GTX Transceiver Clock Generation 13Ethernet PHYConnections U1 Fpga PinRXD5 PHYRXD4RXD4 PHYRXD5USB-to-UART Bridge VbusGround USB Controller 16USB Controller ConnectionsU81 USB Controller DVI Codec 17DVI Controller ConnectionsU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Kb NV Memory Iicsdamain SDAIicsclmain SCL Status LEDs Designator Signal Name Color Label Description16Ethernet PHY Status LEDs Ethernet PHY Status LEDsFpgainitb User I/OFpga Init and Done LEDs Controlled LEDUser LEDs 18User LEDs and Gpio Connector, Directional LEDsUser Pushbutton Switches Detailed Description 21User LED Connections Fpga U1 PinGpio J62 Pin Controlled LED Switch Pin User DIP SwitchUser SMA Gpio UsersmagpionUsersmagpiop J41 Pin LCD Display 16 Character x 2 LinesPower On/Off Slide Switch SW2 SwitchesFpgaprogb Pushbutton SW4 Active-Low Sysaceresetb Pushbutton SW3 Active-Low26System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1M20 Bus Width 26ML605 Configuration ModesMaster BPI Vita 57.1 FMC HPC ConnectorHPC Pin 28VITA 57.1 FMC HPC Connections28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB08N FMCHPCHB09NFMCHPCHB08P FMCHPCHB13PDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d VREFBM2C VadjVIOBM2C Vadj VREFAM2C VadjVita 57.1 FMC LPC Connector LPC Pin 30VITA 57.1 FMC LPC ConnectionsPower Management AC Adapter and Input Power Jack/SwitchDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d 28ML605 Onboard Power Regulators Onboard Power RegulationUCD7230RGWR UCD9240PFCVccintfpga Vccaux29System Monitor External Reference System MonitorSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Function/Type Default Table A-1Default Switch SettingsGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF NET DDR3D9 Appendix C ML605 Master UCFNET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References
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