Xilinx ML605 manual FMCHPCHB09N, FMCHPCHB08P, FMCHPCHB13P, FMCHPCHB08N, FMCHPCHB13N, FMCHPCHB12P

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Chapter 1: ML605 Evaluation Board

Table 1-28:VITA 57.1 FMC HPC Connections (Cont’d)

J64 FMC	Schematic Net Name	U1 FPGA		J64 FMC	Schematic Net Name	U1 FPGA
HPC Pin	Schematic Net Name	Pin		HPC Pin	Schematic Net Name	Pin
HPC Pin		Pin		HPC Pin		Pin

E28	FMC_HPC_HB09_N	AK34		F28	FMC_HPC_HB08_P	AK33

E30	FMC_HPC_HB13_P	AH33		F29	FMC_HPC_HB08_N	AK32

E31	FMC_HPC_HB13_N	AH32		F31	FMC_HPC_HB12_P	AJ31

E33	FMC_HPC_HB19_P	AL31		F32	FMC_HPC_HB12_N	AJ32

E34	FMC_HPC_HB19_N	AK31		F34	FMC_HPC_HB16_P	AH29

				F35	FMC_HPC_HB16_N	AH30


G2	FMC_HPC_CLK1_M2C_P	AP20		H2	FMC_HPC_PRSNT_M2C_L(1)	AP25
G3	FMC_HPC_CLK1_M2C_N	AP21		H4	FMC_HPC_CLK0_M2C_P	K24

G6	FMC_HPC_LA00_CC_P	AF20		H5	FMC_HPC_CLK0_M2C_N	K23

G7	FMC_HPC_LA00_CC_N	AF21		H7	FMC_HPC_LA02_P	AC20

G9	FMC_HPC_LA03_P	AC19		H8	FMC_HPC_LA02_N	AD20

G10	FMC_HPC_LA03_N	AD19		H10	FMC_HPC_LA04_P	AF19

G12	FMC_HPC_LA08_P	AK22		H11	FMC_HPC_LA04_N	AE19

G13	FMC_HPC_LA08_N	AJ22		H13	FMC_HPC_LA07_P	AK21

G15	FMC_HPC_LA12_P	AM21		H14	FMC_HPC_LA07_N	AJ21

G16	FMC_HPC_LA12_N	AL21		H16	FMC_HPC_LA11_P	AM22

G18	FMC_HPC_LA16_P	AP22		H17	FMC_HPC_LA11_N	AN22

G19	FMC_HPC_LA16_N	AN23		H19	FMC_HPC_LA15_P	AM23

G21	FMC_HPC_LA20_P	AK23		H20	FMC_HPC_LA15_N	AL23

G22	FMC_HPC_LA20_N	AL24		H22	FMC_HPC_LA19_P	AN25

G24	FMC_HPC_LA22_P	AP27		H23	FMC_HPC_LA19_N	AN24

G25	FMC_HPC_LA22_N	AP26		H25	FMC_HPC_LA21_P	AN29

G27	FMC_HPC_LA25_P	AN28		H26	FMC_HPC_LA21_N	AP29

G28	FMC_HPC_LA25_N	AM28		H28	FMC_HPC_LA24_P	AN30

G30	FMC_HPC_LA29_P	AL28		H29	FMC_HPC_LA24_N	AM30

G31	FMC_HPC_LA29_N	AK28		H31	FMC_HPC_LA28_P	AK27

G33	FMC_HPC_LA31_P	AL29		H32	FMC_HPC_LA28_N	AJ27

G34	FMC_HPC_LA31_N	AK29		H34	FMC_HPC_LA30_P	AJ24

G36	FMC_HPC_LA33_P	AH23		H35	FMC_HPC_LA30_N	AK24

G37	FMC_HPC_LA33_N	AH24		H37	FMC_HPC_LA32_P	AG25

				H38	FMC_HPC_LA32_N	AG26

60	www.xilinx.com	ML605 Hardware User Guide
		UG534 (v1.2.1) January 21, 2010

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Contents ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optionalRevision History Date Version RevisionTable of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This GuideML605 Evaluation Board Additional InformationFeatures ML605 Evaluation BoardSMA IIC Eeprom 1 KBOverview Fpga Init Fpga DoneBlock Diagram 1ML605 High-Level Block DiagramML605 Features FeatureDetailed Description DDR3 SodimmML605 Evaluation Board ML605 Features Cont’d SgmiiWDW6TP Configuration Virtex-6 XC6VLX240T-1FFG1156 Fpga2Virtex-6 Fpga Configuration Modes M20 Voltage RailsCclk Direction 3Voltage Rails U1 Fpga BankMB DDR3 Memory Sodimm Detailed Description 3Voltage Rails Cont’d U1 Fpga BankVCC1V5FPGA 4DDR3 Sodimm ConnectionsML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI FlashML605 Flash Boot Options FLASHD0 DQ0 FLASHD1 DQ1FLASHD2 DQ2 FLASHD3 DQ3Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Clock Generation Oscillator DifferentialOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location IdentifiersSMA Pin SmarefclknSmarefclkp Multi-Gigabit Transceivers GTX MGTs ICSPCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J428PCIe Edge Connector Connections AA3 PCIERX7P AA4 PCIERX7NPCIE100MMGT0P GTXE1X0Y6SFP Module Connector 11PHY Default Interface Mode Jumper Settings J66 J67 J68 12Board Connections for PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit012Board Connections for PHY Configuration Pins Cont’d Sgmii GTX Transceiver Clock Generation13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111PHYRXD4 RXD4PHYRXD5 RXD5USB-to-UART Bridge VbusGround USB Controller 16USB Controller ConnectionsU81 USB Controller DVI Codec 17DVI Controller ConnectionsU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Kb NV Memory Iicsdamain SDAIicsclmain SCL Designator Signal Name Color Label Description Status LEDsEthernet PHY Status LEDs 16Ethernet PHY Status LEDsUser I/O Fpga Init and Done LEDsControlled LED Fpgainitb18User LEDs and Gpio Connector, Directional LEDs User LEDsUser Pushbutton Switches Detailed Description 21User LED Connections Fpga U1 PinGpio J62 Pin Controlled LED User DIP Switch Switch PinUser SMA Gpio UsersmagpionUsersmagpiop LCD Display 16 Character x 2 Lines J41 PinSwitches Power On/Off Slide Switch SW2Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-LowSystem ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S126ML605 Configuration Modes M20 Bus Width Vita 57.1 FMC HPC Connector Master BPI28VITA 57.1 FMC HPC Connections HPC Pin28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB09N FMCHPCHB08PFMCHPCHB13P FMCHPCHB08NDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d Vadj VIOBM2C VadjVREFAM2C Vadj VREFBM2CVita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC PinPower Management AC Adapter and Input Power Jack/SwitchDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d Onboard Power Regulation 28ML605 Onboard Power RegulatorsUCD9240PFC VccintfpgaVccaux UCD7230RGWRSystem Monitor 29System Monitor External ReferenceSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Table A-1Default Switch Settings Function/Type DefaultGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References