Xilinx manual ML605 Flash Boot Options

Page 21

Detailed Description

ML605 Flash Boot Options

The ML605 has two parallel wired flash memory devices as shown in Figure 1-3. At ML605 power-up, before FPGA configuration, DIP switch S2 switch 2 selects which flash device, U4 (BPI) or U27 (Platform Flash), provides the boot bitstream. Typically S2 switch 2 will be open/OFF to select the U27 Platform Flash. Given that the mode switches (S2 switch 3/M0, switch 4/M1 and switch 5/M2) are set to Slave SelectMAP mode, then U27, driven at 47 MHz, can load a PCIe core bitstream before a host PC motherboard can scan its PCIe slots.When S2 switch 2 is closed/ON at power up, the FPGA will be configured from the BPI flash device U4. Note that U4 address bit A23 is switched by S2 switch 6, which allows the lower or upper half of U4 to be chosen as a data source.

Table 1-5shows the connections and pin numbers for the boot flash devices.

Table 1-5:Platform Flash and BPI Flash Connections

U1 FPGA Pin

Schematic Net Name

U4 BPI Flash

U27 Platform Flash

 

 

 

 

Pin Number

Pin Name

Pin Number

Pin Name

 

 

 

 

 

 

 

 

AL8

FLASH_A0

29

A1

A1

A00

 

 

 

 

 

 

AK8

FLASH_A1

25

A2

B1

A01

 

 

 

 

 

 

AC9

FLASH_A2

24

A3

C1

A02

 

 

 

 

 

 

AD10

FLASH_A3

23

A4

D1

A03

 

 

 

 

 

 

C8

FLASH_A4

22

A5

D2

A04

 

 

 

 

 

 

B8

FLASH_A5

21

A6

A2

A05

 

 

 

 

 

 

E9

FLASH_A6

20

A7

C2

A06

 

 

 

 

 

 

E8

FLASH_A7

19

A8

A3

A07

 

 

 

 

 

 

A8

FLASH_A8

8

A9

B3

A08

 

 

 

 

 

 

A9

FLASH_A9

7

A10

C3

A09

 

 

 

 

 

 

D9

FLASH_A10

6

A11

D3

A10

 

 

 

 

 

 

C9

FLASH_A11

5

A12

C4

A11

 

 

 

 

 

 

D10

FLASH_A12

4

A13

A5

A12

 

 

 

 

 

 

C10

FLASH_A13

3

A14

B5

A13

 

 

 

 

 

 

F10

FLASH_A14

2

A15

C5

A14

 

 

 

 

 

 

F9

FLASH_A15

1

A16

D7

A15

 

 

 

 

 

 

AH8

FLASH_A16

55

A17

D8

A16

 

 

 

 

 

 

AG8

FLASH_A17

18

A18

A7

A17

 

 

 

 

 

 

AP9

FLASH_A18

17

A19

B7

A18

 

 

 

 

 

 

AN9

FLASH_A19

16

A20

C7

A19

 

 

 

 

 

 

AF10

FLASH_A20

11

A21

C8

A20

 

 

 

 

 

 

AF9

FLASH_A21

10

A22

A8

A21

 

 

 

 

 

 

AL9

FLASH_A22

9

A23

G1

A22

 

 

 

 

 

 

AA23

FLASH_A23

26

A24

NC

A23

 

 

 

 

 

 

ML605 Hardware User Guide

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UG534 (v1.2.1) January 21, 2010

 

 

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Contents UG534 v1.2.1 January 21, 2010 optional ML605 Hardware User GuideDate Version Revision Revision HistoryTable of Contents ML605 Hardware User Guide About This Guide Preface About This Guide Additional Support ResourcesAdditional Information ML605 Evaluation BoardML605 Evaluation Board FeaturesSMA IIC Eeprom 1 KBFpga Init Fpga Done Overview1ML605 High-Level Block Diagram Block DiagramFeature ML605 FeaturesDetailed Description DDR3 SodimmML605 Evaluation Board ML605 Features Cont’d SgmiiWDW6TP Virtex-6 XC6VLX240T-1FFG1156 Fpga ConfigurationVoltage Rails 2Virtex-6 Fpga Configuration Modes M20Cclk Direction 3Voltage Rails U1 Fpga BankDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank MB DDR3 Memory SodimmVCC1V5FPGA 4DDR3 Sodimm ConnectionsDDR3A9 ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’dDDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref MB Linear BPI Flash Mb Platform Flash XLML605 Flash Boot Options FLASHD1 DQ1 FLASHD0 DQ0FLASHD2 DQ2 FLASHD3 DQ3Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Clock Generation Oscillator DifferentialOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers 8ML605 Oscillator Pin 1 Location Identifiers SMA Connectors DifferentialSMA Pin SmarefclknSmarefclkp ICS Multi-Gigabit Transceivers GTX MGTs12PCIe Lane Size Select Jumper J42 PCI Express Endpoint Connectivity8PCIe Edge Connector Connections AA4 PCIERX7N AA3 PCIERX7PPCIE100MMGT0P GTXE1X0Y6SFP Module Connector 12Board Connections for PHY Configuration Pins 11PHY Default Interface Mode Jumper Settings J66 J67 J6811 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0Sgmii GTX Transceiver Clock Generation 12Board Connections for PHY Configuration Pins Cont’d13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111RXD4 PHYRXD4PHYRXD5 RXD5USB-to-UART Bridge VbusGround USB Controller 16USB Controller ConnectionsU81 USB Controller DVI Codec 17DVI Controller ConnectionsU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Kb NV Memory Iicsdamain SDAIicsclmain SCL Status LEDs Designator Signal Name Color Label Description16Ethernet PHY Status LEDs Ethernet PHY Status LEDsFpga Init and Done LEDs User I/OControlled LED FpgainitbUser LEDs 18User LEDs and Gpio Connector, Directional LEDsUser Pushbutton Switches Detailed Description 21User LED Connections Fpga U1 PinGpio J62 Pin Controlled LED Switch Pin User DIP SwitchUser SMA Gpio UsersmagpionUsersmagpiop J41 Pin LCD Display 16 Character x 2 LinesPower On/Off Slide Switch SW2 SwitchesFpgaprogb Pushbutton SW4 Active-Low Sysaceresetb Pushbutton SW3 Active-Low26System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1M20 Bus Width 26ML605 Configuration ModesMaster BPI Vita 57.1 FMC HPC ConnectorHPC Pin 28VITA 57.1 FMC HPC Connections28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB08P FMCHPCHB09NFMCHPCHB13P FMCHPCHB08NDetailed Description 28VITA 57.1 FMC HPC Connections Cont’d VIOBM2C Vadj VadjVREFAM2C Vadj VREFBM2CVita 57.1 FMC LPC Connector LPC Pin 30VITA 57.1 FMC LPC ConnectionsPower Management AC Adapter and Input Power Jack/SwitchDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d 28ML605 Onboard Power Regulators Onboard Power RegulationVccintfpga UCD9240PFCVccaux UCD7230RGWR29System Monitor External Reference System MonitorSystem Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration OptionsML605 Evaluation Board Function/Type Default Table A-1Default Switch SettingsGmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF NET DDR3D9 Appendix C ML605 Master UCFNET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References