Texas Instruments 3138 155 232931 manual Avddadc

Page 16

 

 

 

 

CC2420

 

 

 

 

Pin

Pin Name

Pin type

Pin Description

16

NC

-

Not Connected

17

AVDD_ADC

Power (analog)

1.8

V Power supply for analog parts of ADCs and DACs

18

DVDD_ADC

Power (digital)

1.8

V Power supply for digital parts of receive ADCs

19

DGND_GUARD

Ground (digital)

Ground connection for digital noise isolation

20

DGUARD

Power (digital)

1.8

V Power supply connection for digital noise isolation

21

RESETn

Digital Input

Asynchronous, active low digital reset

22

DGND

Ground (digital)

Ground connection for digital core and pads

23

DSUB_PADS

Ground (digital)

Substrate connection for digital pads

24

DSUB_CORE

Ground (digital)

Substrate connection for digital modules

25

DVDD3.3

Power (digital)

3.3

V Power supply for digital I/Os

26

DVDD1.8

Power (digital)

1.8

V Power supply for digital core

27

SFD

Digital output

SFD (Start of Frame Delimiter) / digital mux output

28

CCA

Digital output

CCA (Clear Channel Assessment) / digital mux output

29

FIFOP

Digital output

Active when number of bytes in FIFO exceeds threshold /

 

 

 

serial RF clock output in test mode

30

FIFO

Digital I/O

Active when data in FIFO /

 

 

 

serial RF data input / output in test mode

31

CSn

Digital input

SPI Chip select, active low

32

SCLK

Digital input

SPI Clock input, up to 10 MHz

33

SI

Digital input

SPI Slave Input. Sampled on the positive edge of SCLK

34

SO

Digital output

SPI Slave Output. Updated on the negative edge of SCLK.

 

 

(tristate)

Tristate when CSn high.

35

DVDD_RAM

Power (digital)

1.8

V Power supply for digital RAM

36

NC

-

Not Connected

37

AVDD_XOSC16

Power (analog)

1.8

V crystal oscillator power supply

38

XOSC16_Q2

Analog I/O

16 MHz Crystal oscillator pin 2

39

XOSC16_Q1

Analog I/O

16 MHz Crystal oscillator pin 1 or external clock input

40

NC

-

Not Connected

41

VREG_EN

Digital input

Voltage regulator enable, active high, held at VREG_IN

 

 

 

voltage level when active. Note that VREG_EN is relative

 

 

 

VREG_IN, not DVDD3.3.

42

VREG_OUT

Power output

Voltage regulator 1.8 V power supply output

43

VREG_IN

Power (analog)

Voltage regulator 2.1 to 3.6 V power supply input

44

AVDD_IF1

Power (analog)

1.8

V Power supply for transmit / receive IF chain

45

R_BIAS

Analog output

External precision resistor, 43 kΩ, ± 1 %

46

ATEST2

Analog I/O

Analog test I/O for prototype and production testing

47

ATEST1

Analog I/O

Analog test I/O for prototype and production testing

48

AVDD_CHP

Power (analog)

1.8

V Power supply for phase detector and charge pump

NOTES:

The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the chip.

SWRS041B

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Contents Applications Key FeaturesProduct Description Table of contents RF Data Buffering Ordering Information General Information Abbreviations ITU-TReferences Features Absolute Maximum Ratings Operating ConditionsParameter Min Max Units Condition Parameter Min Typ Max Units ConditionElectrical Specifications OverallTransmit Section Parameter Min Typ Max Unit Condition / NoteReceive Section If Section Rssi / Carrier SenseFrequency Synthesizer Section Digital Inputs/Outputs VDDPower Supply Battery MonitorVoltage Regulator CC2420 Pin Assignment Pin Pin Name Pin type Pin DescriptionAvddadc CC2420 simplified block diagram Circuit DescriptionCC2420 Power supply decoupling and filtering Application CircuitInput / output matching Bias resistorOverview of external components DescriptionTransceiver Transceiver Bill of materials for the application circuits Symbol Chip sequence C0, C1, C2, … , C31 Ieee 802.15.4 Modulation FormatConfiguration Overview PhaseEvaluation Software SmartRF Studio user interfacePin configuration 13 4-wire Serial Configuration and Data InterfaceRegister access SPI timing specification Status byte Parameter Symbol Min Max Units ConditionsRAM access Configuration registers write and read operations via SPI Multiple SPI access CC2420 RAM Memory Space Fifo accessAddress Byte Ordering Name Description Configuration interface Microcontroller Interface and Pin DescriptionReceive mode Rxfifo overflowPin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Demodulator Simplified Block Diagram Frame FormatTransmitted Synchronisation Header Length field MAC protocol data unitFormat of the Frame Control Field FCF Frame check sequence Buffered receive mode Buffered transmit modeRF Data Buffering Unbuffered, serial mode FifopAddress Recognition Acknowledge FramesAcknowledge frame format Radio control state machine Radio control states MAC Security Operations Encryption and Authentication KeysNonce / counter Ieee 802.15.4 NonceCC2420 Security Flag Byte Stand-alone encryption In-line security operationsCBC-MAC CTR mode encryption / decryption21.7 CCM Linear if and AGC Settings Mode LMIC TimeRssi / Energy Detection TimingValue Link Quality IndicationRF Level dBm Clear Channel Assessment Frequency and Channel ProgrammingOutput Power Programming VCO and PLL Self-CalibrationVoltage Regulator 27.1 VCOBattery Monitor Voltage regulator, simplified schematicCrystal Oscillator Input / Output Matching Transmitter Test ModesCrystal oscillator component values Unmodulated carrierCC2420 Modulated spectrum plot System Considerations and Guidelines Low-cost systems Battery operated systemsBER / PER measurements PCB Layout Recommendations Antenna ConsiderationsCC2420 Configuration Registers Address Register Register type DescriptionConfiguration registers overview SaesMain 0x10 Main Control Register Bit Field Name ResetXOSC16MBYPASS Reservedframemode Pancoordinator Adrdecode MDMCTRL0 0x11 Modem Control RegisterCCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength MDMCTRL1 0x12- Modem Control Register Rssi 0x13 Rssi and CCA Status and Control RegisterCORRTHR40 Demodavgmode Modulationmode RSSIVAL70Syncword 0x14 Sync Word Txctrl 0x15 Transmit Control RegisterRXCTRL0 0x16 Receive control register RXMIXBUFCUR10RXCTRL1 0x17 Receive control register Fsctrl 0x18 Frequency Synthesizer Control and Status Caldone Calrunning Locklength LockstatusSECCTRL0 0x19 Security Control Register SECMODE10Battmon 0x1B Battery Monitor Control register SECCTRL1 0x1A Security Control RegisterSectxl Secrxl Battmonok Battmonen BattmonvoltageIOCFG0 0x1C I/O Configuration Register IOCFG1 0x1D I/O Configuration RegisterManfidl 0x1E Manufacturer ID, Lower 16 Bit HSSDSRC20 SFDMUX40 CCAMUX40Manfidh 0x1F Manufacturer ID, Upper 16 Bit Fsmtc 0x20 Finite state machine time constantsManand 0x21 Manual signal and override register1 Isused = is * Isandmask + IsormaskManor 0x22 Manual signal or override register Agcctrl 0x23 AGC ControlVgagainoe LnamixgainmodeoAGCTST1 0x25 AGC Test Register AGCTST0 0x24 AGC Test RegisterAGCTST2 0x26 AGC Test Register FSTST1 0x28 Frequency Synthesizer Test Register FSTST0 0x27 Frequency Synthesizer Test RegisterFSTST2 0x29 Frequency Synthesizer Test Register Rxbpftst 0x2B Receiver Bandpass Filters Test Register FSTST3 0x2A Frequency Synthesizer Test RegisterFsmstate 0x2C Finite state machine information Adctst 0x2D ADC Test Register AdcclockdisableDactst 0x2E DAC Test Register Oscillator must be running for accessing the Rxfifo Toptst 0x2F Top Level Test RegisterTxfifo 0x3E Transmit Fifo Byte register Rxfifo 0x3F Receive Fifo Byte registerCCA test signal select table Test Output SignalsSignal output on CCA pin Description SFD test signal select table Signal output on SFD pin DescriptionPackage Description QLP Quad Leadless Package QLPRecommended layout for package QLP Package thermal propertiesSoldering information Thermal resistance40.3 Plastic tube specification 40.4 Carrier tape and reel specificationTube Specification Tape and Reel Specification42.1 Document History General InformationRevision Date Description/Changes Data Sheet Identification Product Status Definition Product Status DefinitionsTI Worldwide Technical Support Internet Address InformationProduct Information Centers 2007, Texas Instruments. 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