Texas Instruments 3138 155 232931 manual Pin activity examples during receive

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Data received over RF

	Address	SFD Pin
	recognition OK	SFD Pin
	recognition OK
		FIFO Pin

FIFOP Pin, if threshold higher than frame length

FIFOP Pin, if threshold lower than frame length

Data received over RF

	Address	SFD Pin
	recognition fails	SFD Pin
	recognition fails
		FIFO Pin
		FIFOP Pin

CC2420

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Length

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Preamble	SFD	Length	MAC Protocol Data Unit (MPDU) with wrong address

Figure 13. Pin activity examples during receive

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SO	Status	Length	PSDU0	PSDU1	PSDU2	PSDU3	PSDU4	PSDU5	RSSI	FCS/Corr

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Figure 14. Example of pin activity when reading RXFIFO.

14.4 Transmit mode

During transmit the FIFO and FIFOP pins are still only related to the RXFIFO. The SFD pin is however active during transmission of a data frame, as shown in Figure 15.

The SFD pin goes active when the SFD field has been completely transmitted. It goes inactive again when the complete MPDU (as defined by the length field) has been transmitted or if an underflow is

detected. See the RF Data Buffering section on page 39 for more information on TXFIFO underflow.

As can be seen from comparing Figure 13 and Figure 15, the SFD pin behaves very similarly during reception and transmission of a data frame. If the SFD pins of the transmitter and the receiver are compared during the transmission of a data frame, a small delay of approximately 2 µs can be seen because of bandwidth limitations in both the transmitter and the receiver.

SWRS041B

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Contents Applications Key FeaturesProduct Description Table of contents RF Data Buffering Ordering Information General Information Abbreviations ITU-TReferences Features Parameter Min Max Units Condition Absolute Maximum RatingsOperating Conditions Parameter Min Typ Max Units ConditionTransmit Section Electrical SpecificationsOverall Parameter Min Typ Max Unit Condition / NoteReceive Section If Section Rssi / Carrier SenseFrequency Synthesizer Section Digital Inputs/Outputs VDDPower Supply Battery MonitorVoltage Regulator CC2420 Pin Assignment Pin Pin Name Pin type Pin DescriptionAvddadc CC2420 simplified block diagram Circuit DescriptionCC2420 Input / output matching Power supply decoupling and filteringApplication Circuit Bias resistorOverview of external components DescriptionTransceiver Transceiver Bill of materials for the application circuits Symbol Chip sequence C0, C1, C2, … , C31 Ieee 802.15.4 Modulation FormatConfiguration Overview PhaseEvaluation Software SmartRF Studio user interfacePin configuration 13 4-wire Serial Configuration and Data InterfaceRegister access SPI timing specification Status byte Parameter Symbol Min Max Units ConditionsRAM access Configuration registers write and read operations via SPI Multiple SPI access CC2420 RAM Memory Space Fifo accessAddress Byte Ordering Name Description Configuration interface Microcontroller Interface and Pin DescriptionReceive mode Rxfifo overflowPin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Demodulator Simplified Block Diagram Frame FormatTransmitted Synchronisation Header Length field MAC protocol data unitFormat of the Frame Control Field FCF Frame check sequence Buffered receive mode Buffered transmit modeRF Data Buffering Unbuffered, serial mode FifopAddress Recognition Acknowledge FramesAcknowledge frame format Radio control state machine Radio control states Nonce / counter MAC Security Operations Encryption and AuthenticationKeys Ieee 802.15.4 NonceCC2420 Security Flag Byte Stand-alone encryption In-line security operationsCBC-MAC CTR mode encryption / decryption21.7 CCM Rssi / Energy Detection Linear if and AGC SettingsMode LMIC Time TimingValue Link Quality IndicationRF Level dBm Clear Channel Assessment Frequency and Channel ProgrammingVoltage Regulator Output Power ProgrammingVCO and PLL Self-Calibration 27.1 VCOBattery Monitor Voltage regulator, simplified schematicCrystal Oscillator Crystal oscillator component values Input / Output MatchingTransmitter Test Modes Unmodulated carrierCC2420 Modulated spectrum plot System Considerations and Guidelines Low-cost systems Battery operated systemsBER / PER measurements PCB Layout Recommendations Antenna ConsiderationsCC2420 Configuration Registers Address Register Register type DescriptionConfiguration registers overview SaesMain 0x10 Main Control Register Bit Field Name ResetXOSC16MBYPASS Reservedframemode Pancoordinator Adrdecode MDMCTRL0 0x11 Modem Control RegisterCCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength CORRTHR40 Demodavgmode Modulationmode MDMCTRL1 0x12- Modem Control RegisterRssi 0x13 Rssi and CCA Status and Control Register RSSIVAL70Syncword 0x14 Sync Word Txctrl 0x15 Transmit Control RegisterRXCTRL0 0x16 Receive control register RXMIXBUFCUR10RXCTRL1 0x17 Receive control register Fsctrl 0x18 Frequency Synthesizer Control and Status Caldone Calrunning Locklength LockstatusSECCTRL0 0x19 Security Control Register SECMODE10Sectxl Secrxl Battmon 0x1B Battery Monitor Control registerSECCTRL1 0x1A Security Control Register Battmonok Battmonen BattmonvoltageManfidl 0x1E Manufacturer ID, Lower 16 Bit IOCFG0 0x1C I/O Configuration RegisterIOCFG1 0x1D I/O Configuration Register HSSDSRC20 SFDMUX40 CCAMUX40Manfidh 0x1F Manufacturer ID, Upper 16 Bit Fsmtc 0x20 Finite state machine time constantsManand 0x21 Manual signal and override register1 Isused = is * Isandmask + IsormaskVgagainoe Manor 0x22 Manual signal or override registerAgcctrl 0x23 AGC Control LnamixgainmodeoAGCTST1 0x25 AGC Test Register AGCTST0 0x24 AGC Test RegisterAGCTST2 0x26 AGC Test Register FSTST1 0x28 Frequency Synthesizer Test Register FSTST0 0x27 Frequency Synthesizer Test RegisterFSTST2 0x29 Frequency Synthesizer Test Register Rxbpftst 0x2B Receiver Bandpass Filters Test Register FSTST3 0x2A Frequency Synthesizer Test RegisterFsmstate 0x2C Finite state machine information Adctst 0x2D ADC Test Register AdcclockdisableDactst 0x2E DAC Test Register Txfifo 0x3E Transmit Fifo Byte register Oscillator must be running for accessing the RxfifoToptst 0x2F Top Level Test Register Rxfifo 0x3F Receive Fifo Byte registerCCA test signal select table Test Output SignalsSignal output on CCA pin Description SFD test signal select table Signal output on SFD pin DescriptionPackage Description QLP Quad Leadless Package QLPSoldering information Recommended layout for package QLPPackage thermal properties Thermal resistanceTube Specification 40.3 Plastic tube specification40.4 Carrier tape and reel specification Tape and Reel Specification42.1 Document History General InformationRevision Date Description/Changes Data Sheet Identification Product Status Definition Product Status DefinitionsTI Worldwide Technical Support Internet Address InformationProduct Information Centers 2007, Texas Instruments. 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