Texas Instruments 3138 155 232931 manual Unbuffered, serial mode, Fifop

Page 40

CC2420

Multiple data frames may be in the RXFIFO simultaneously, as long as the total number of bytes does not exceed 128.

See the RXFIFO overflow section on page 33 for details on how a RXFIFO overflow is detected and signalled.

17.3 Unbuffered, serial mode

Unbuffered mode should be used for evaluation / debugging purposes only. Buffered mode is recommended for all applications.

In unbuffered mode, the FIFO and FIFOP pins are reconfigured as data and data clock pins. The TXFIFO and RXFIFO buffers are not used in this mode. A synchronous data clock is provided by CC2420 at the FIFOP pin, and the FIFO pin is used as data input/output. The FIFOP clock frequency is 250 kHz when active. This is illustrated in Figure 22.

In serial transmit mode

(MDMCTRL1.TX_MODE=1),a synchronisation sequence is inserted at the start of each frame by hardware, as in buffered mode. Data is sampled by CC2420 on the positive edge of FIFOP and should be updated by the microcontroller on the negative edge of FIFOP. See Figure 22 for an illustration of the timing in serial transmit mode. The SFD and CCA pins retain their normal operation also in serial mode. CC2420 will remain in serial transmit mode until transmission is turned off manually.

In serial receive mode

(MDMCTRL1.RX_MODE=1)byte synchronisation is still performed by CC2420. This means that the FIFOP clock pin will remain inactive until a start of frame delimiter has been detected.

Incoming / outgoing

Preamble

SFD

s0

s1

s2

RF data

 

 

 

 

 

Transmit mode:

 

4 us

 

 

 

 

 

 

 

 

FIFOP

 

 

 

 

 

FIFO (from uC)

 

b0 b1 b2 b3

b4 b5 b6 b7 b8

b9 b10 b11 b8

b9 b10 b11

Receive mode:

FIFOP

FIFO (from CC2420)

b0 b1 b2 b3 b4

Figure 22. Unbuffered test mode, pin activity

SWRS041B

Page 40 of 89

Page 39 Page 41
Image 40
Page 39 Page 41
Contents Applications Key FeaturesProduct Description Table of contents RF Data Buffering Ordering Information General Information Abbreviations ITU-TReferences Features Absolute Maximum Ratings Operating ConditionsParameter Min Max Units Condition Parameter Min Typ Max Units ConditionElectrical Specifications OverallTransmit Section Parameter Min Typ Max Unit Condition / NoteReceive Section If Section Rssi / Carrier SenseFrequency Synthesizer Section Digital Inputs/Outputs VDDPower Supply Battery MonitorVoltage Regulator CC2420 Pin Assignment Pin Pin Name Pin type Pin DescriptionAvddadc CC2420 simplified block diagram Circuit DescriptionCC2420 Power supply decoupling and filtering Application CircuitInput / output matching Bias resistorOverview of external components DescriptionTransceiver Transceiver Bill of materials for the application circuits Symbol Chip sequence C0, C1, C2, … , C31 Ieee 802.15.4 Modulation FormatConfiguration Overview PhaseEvaluation Software SmartRF Studio user interfacePin configuration 13 4-wire Serial Configuration and Data InterfaceRegister access SPI timing specification Status byte Parameter Symbol Min Max Units ConditionsRAM access Configuration registers write and read operations via SPI Multiple SPI access CC2420 RAM Memory Space Fifo accessAddress Byte Ordering Name Description Configuration interface Microcontroller Interface and Pin DescriptionReceive mode Rxfifo overflowPin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Demodulator Simplified Block Diagram Frame FormatTransmitted Synchronisation Header Length field MAC protocol data unitFormat of the Frame Control Field FCF Frame check sequence Buffered receive mode Buffered transmit modeRF Data Buffering Unbuffered, serial mode FifopAddress Recognition Acknowledge FramesAcknowledge frame format Radio control state machine Radio control states MAC Security Operations Encryption and Authentication KeysNonce / counter Ieee 802.15.4 NonceCC2420 Security Flag Byte Stand-alone encryption In-line security operationsCBC-MAC CTR mode encryption / decryption21.7 CCM Linear if and AGC Settings Mode LMIC TimeRssi / Energy Detection TimingValue Link Quality IndicationRF Level dBm Clear Channel Assessment Frequency and Channel ProgrammingOutput Power Programming VCO and PLL Self-CalibrationVoltage Regulator 27.1 VCOBattery Monitor Voltage regulator, simplified schematicCrystal Oscillator Input / Output Matching Transmitter Test ModesCrystal oscillator component values Unmodulated carrierCC2420 Modulated spectrum plot System Considerations and Guidelines Low-cost systems Battery operated systemsBER / PER measurements PCB Layout Recommendations Antenna ConsiderationsCC2420 Configuration Registers Address Register Register type DescriptionConfiguration registers overview SaesMain 0x10 Main Control Register Bit Field Name ResetXOSC16MBYPASS Reservedframemode Pancoordinator Adrdecode MDMCTRL0 0x11 Modem Control RegisterCCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength MDMCTRL1 0x12- Modem Control Register Rssi 0x13 Rssi and CCA Status and Control RegisterCORRTHR40 Demodavgmode Modulationmode RSSIVAL70Syncword 0x14 Sync Word Txctrl 0x15 Transmit Control RegisterRXCTRL0 0x16 Receive control register RXMIXBUFCUR10RXCTRL1 0x17 Receive control register Fsctrl 0x18 Frequency Synthesizer Control and Status Caldone Calrunning Locklength LockstatusSECCTRL0 0x19 Security Control Register SECMODE10Battmon 0x1B Battery Monitor Control register SECCTRL1 0x1A Security Control RegisterSectxl Secrxl Battmonok Battmonen BattmonvoltageIOCFG0 0x1C I/O Configuration Register IOCFG1 0x1D I/O Configuration RegisterManfidl 0x1E Manufacturer ID, Lower 16 Bit HSSDSRC20 SFDMUX40 CCAMUX40Manfidh 0x1F Manufacturer ID, Upper 16 Bit Fsmtc 0x20 Finite state machine time constantsManand 0x21 Manual signal and override register1 Isused = is * Isandmask + IsormaskManor 0x22 Manual signal or override register Agcctrl 0x23 AGC ControlVgagainoe LnamixgainmodeoAGCTST1 0x25 AGC Test Register AGCTST0 0x24 AGC Test RegisterAGCTST2 0x26 AGC Test Register FSTST1 0x28 Frequency Synthesizer Test Register FSTST0 0x27 Frequency Synthesizer Test RegisterFSTST2 0x29 Frequency Synthesizer Test Register Rxbpftst 0x2B Receiver Bandpass Filters Test Register FSTST3 0x2A Frequency Synthesizer Test RegisterFsmstate 0x2C Finite state machine information Adctst 0x2D ADC Test Register AdcclockdisableDactst 0x2E DAC Test Register Oscillator must be running for accessing the Rxfifo Toptst 0x2F Top Level Test RegisterTxfifo 0x3E Transmit Fifo Byte register Rxfifo 0x3F Receive Fifo Byte registerCCA test signal select table Test Output SignalsSignal output on CCA pin Description SFD test signal select table Signal output on SFD pin DescriptionPackage Description QLP Quad Leadless Package QLPRecommended layout for package QLP Package thermal propertiesSoldering information Thermal resistance40.3 Plastic tube specification 40.4 Carrier tape and reel specificationTube Specification Tape and Reel Specification42.1 Document History General InformationRevision Date Description/Changes Data Sheet Identification Product Status Definition Product Status DefinitionsTI Worldwide Technical Support Internet Address InformationProduct Information Centers 2007, Texas Instruments. All rights reserved Important Notice
Top Page Image Contents