Texas Instruments 3138 155 232931 manual Address Recognition, Acknowledge Frames

Page 41

18 Address Recognition

CC2420 includes hardware support for address recognition, as specified in [1]. Hardware address recognition may be enabled / disabled using the MDMCTRL0.ADR_DECODE control bit.

Address recognition is based on the following requirements, listed from section 7.5.6.2 in [1]:

•The frame type subfield shall not contain an illegal frame type

•If the frame type indicates that the frame is a beacon frame, the source PAN identifier shall match macPANId unless macPANId is equal to 0xFFFF, in which case the beacon frame shall be accepted regardless of the source PAN identifier.

•If a destination PAN identifier is included in the frame, it shall match macPANId or shall be the

broadcast PAN identifier (0xFFFF).

•If a short destination address is included in the frame, it shall match either macShortAddress or the broadcast address (0xFFFF). Otherwise if an extended destination address is included in the frame, it shall match aExtendedAddress.

•If only source addressing fields are included in a data or MAC command frame, the frame shall only be accepted if the device is a PAN coordinator and the source

CC2420

PAN identifier matches macPANId.

If any of the above requirements are not satisfied and address recognition is enabled, CC2420 will disregard the incoming frame and flush the data from the RXFIFO. Only data from the rejected frame is flushed, data from previously accepted frames may still be in the

RXFIFO.

The IOCFG0.BCN_ACCEPT control bit must be set when the PAN identifier programmed into CC2420 RAM is equal to 0xFFFF and cleared otherwise. This particularly applies to active and passive scans as defined by [1], which requires all received beacons to be processed by the MAC sublayer.

Incoming frames with reserved frame types (FCF frame type subfield is 4, 5, 6 or

7)is however accepted if the

RESERVED_FRAME_MODE control bit in

MDMCTRL0 is set. In this case, no further address recognition is performed on these frames. This option is included for future expansions of the IEEE 802.15.4 standard.

If a frame is rejected, CC2420 will only start searching for a new frame after the rejected frame has been completely received (as defined by the length field) to avoid detecting false SFDs within the frame.

The MDMCTRL0.PAN_COORDINATOR control bit must be correctly set, since parts of the address recognition procedure requires knowledge about whether the current device is a PAN coordinator or not.

19 Acknowledge Frames

CC2420 includes hardware support for transmitting acknowledge frames, as specified in [1]. Figure 23 shows the format of the acknowledge frame.

If MDMCTRL0.AUTOACK is enabled, an acknowledge frame is transmitted for all incoming frames accepted by the address

recognition with the acknowledge request flag set and a valid CRC. AUTOACK therefore does not make sense unless also ADR_DECODE and AUTOCRC are enabled. The sequence number is copied from the incoming frame.

SWRS041B

Page 41 of 89

Page 40 Page 42
Image 41
Page 40 Page 42
Contents Product Description Key FeaturesApplications Table of contents RF Data Buffering Ordering Information General Information ITU-T AbbreviationsReferences Features Operating Conditions Absolute Maximum RatingsParameter Min Max Units Condition Parameter Min Typ Max Units ConditionOverall Electrical SpecificationsTransmit Section Parameter Min Typ Max Unit Condition / NoteReceive Section Frequency Synthesizer Section Rssi / Carrier SenseIf Section VDD Digital Inputs/OutputsVoltage Regulator Battery MonitorPower Supply CC2420 Pin Pin Name Pin type Pin Description Pin AssignmentAvddadc Circuit Description CC2420 simplified block diagramCC2420 Application Circuit Power supply decoupling and filteringInput / output matching Bias resistorDescription Overview of external componentsTransceiver Transceiver Bill of materials for the application circuits Ieee 802.15.4 Modulation Format Symbol Chip sequence C0, C1, C2, … , C31Phase Configuration OverviewSmartRF Studio user interface Evaluation SoftwareRegister access 13 4-wire Serial Configuration and Data InterfacePin configuration Parameter Symbol Min Max Units Conditions SPI timing specification Status byteRAM access Configuration registers write and read operations via SPI Address Byte Ordering Name Description CC2420 RAM Memory Space Fifo accessMultiple SPI access Microcontroller Interface and Pin Description Configuration interfaceRxfifo overflow Receive modePin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Frame Format Demodulator Simplified Block DiagramMAC protocol data unit Transmitted Synchronisation Header Length fieldFormat of the Frame Control Field FCF Frame check sequence RF Data Buffering Buffered transmit modeBuffered receive mode Fifop Unbuffered, serial modeAcknowledge Frames Address RecognitionAcknowledge frame format Radio control state machine Radio control states Keys MAC Security Operations Encryption and AuthenticationNonce / counter Ieee 802.15.4 NonceIn-line security operations CC2420 Security Flag Byte Stand-alone encryption21.7 CCM CTR mode encryption / decryptionCBC-MAC Mode LMIC Time Linear if and AGC SettingsRssi / Energy Detection TimingRF Level dBm Link Quality IndicationValue Frequency and Channel Programming Clear Channel AssessmentVCO and PLL Self-Calibration Output Power ProgrammingVoltage Regulator 27.1 VCOVoltage regulator, simplified schematic Battery MonitorCrystal Oscillator Transmitter Test Modes Input / Output MatchingCrystal oscillator component values Unmodulated carrierCC2420 Modulated spectrum plot System Considerations and Guidelines BER / PER measurements Battery operated systemsLow-cost systems Antenna Considerations PCB Layout RecommendationsCC2420 Address Register Register type Description Configuration RegistersSaes Configuration registers overviewXOSC16MBYPASS Bit Field Name ResetMain 0x10 Main Control Register CCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength MDMCTRL0 0x11 Modem Control RegisterReservedframemode Pancoordinator Adrdecode Rssi 0x13 Rssi and CCA Status and Control Register MDMCTRL1 0x12- Modem Control RegisterCORRTHR40 Demodavgmode Modulationmode RSSIVAL70Txctrl 0x15 Transmit Control Register Syncword 0x14 Sync WordRXMIXBUFCUR10 RXCTRL0 0x16 Receive control registerRXCTRL1 0x17 Receive control register Caldone Calrunning Locklength Lockstatus Fsctrl 0x18 Frequency Synthesizer Control and StatusSECMODE10 SECCTRL0 0x19 Security Control RegisterSECCTRL1 0x1A Security Control Register Battmon 0x1B Battery Monitor Control registerSectxl Secrxl Battmonok Battmonen BattmonvoltageIOCFG1 0x1D I/O Configuration Register IOCFG0 0x1C I/O Configuration RegisterManfidl 0x1E Manufacturer ID, Lower 16 Bit HSSDSRC20 SFDMUX40 CCAMUX40Fsmtc 0x20 Finite state machine time constants Manfidh 0x1F Manufacturer ID, Upper 16 BitIsused = is * Isandmask + Isormask Manand 0x21 Manual signal and override register1Agcctrl 0x23 AGC Control Manor 0x22 Manual signal or override registerVgagainoe LnamixgainmodeoAGCTST2 0x26 AGC Test Register AGCTST0 0x24 AGC Test RegisterAGCTST1 0x25 AGC Test Register FSTST2 0x29 Frequency Synthesizer Test Register FSTST0 0x27 Frequency Synthesizer Test RegisterFSTST1 0x28 Frequency Synthesizer Test Register Fsmstate 0x2C Finite state machine information FSTST3 0x2A Frequency Synthesizer Test RegisterRxbpftst 0x2B Receiver Bandpass Filters Test Register Dactst 0x2E DAC Test Register AdcclockdisableAdctst 0x2D ADC Test Register Toptst 0x2F Top Level Test Register Oscillator must be running for accessing the RxfifoTxfifo 0x3E Transmit Fifo Byte register Rxfifo 0x3F Receive Fifo Byte registerSignal output on CCA pin Description Test Output SignalsCCA test signal select table Signal output on SFD pin Description SFD test signal select tableQuad Leadless Package QLP Package Description QLPPackage thermal properties Recommended layout for package QLPSoldering information Thermal resistance40.4 Carrier tape and reel specification 40.3 Plastic tube specificationTube Specification Tape and Reel SpecificationRevision Date Description/Changes General Information42.1 Document History Product Status Definitions Data Sheet Identification Product Status DefinitionProduct Information Centers Address InformationTI Worldwide Technical Support Internet 2007, Texas Instruments. All rights reserved Important Notice
Top Page Image Contents