Texas Instruments 3138 155 232931 manual FSTST3 0x2A Frequency Synthesizer Test Register

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CC2420

FSTST3 (0x2A) - Frequency Synthesizer Test Register 3

Bit	Field Name	Reset	R/W
15	CHP_CAL_DISABLE	1	R/W
14	CHP_CURRENT_OE	0	R/W

13	CHP_TEST_UP	0	R/W
12	CHP_TEST_DN	0	R/W
11	CHP_DISABLE	0	R/W

10	PD_DELAY	0	R/W

9:8	CHP_STEP_PERIOD[1:0]	2	R/W

7:4	STOP_CHP_CURRENT[3:0]	13	R/W

3:0	START_CHP_CURRENT[3:0]	13	R/W

Description

Disable charge pump during VCO calibration when set.

Charge pump current override enable

0 : Charge pump current set by calibration

1 : Charge pump current set by START_CHP_CURRENT

Forces the CHP to output "up" current when set

Forces the CHP to output "down" current when set

Set to manually disable charge pump by masking the up and down pulses from the phase-detector.

Selects short or long reset delay in phase detector:

0:Short reset delay

1:Long reset delay

The charge pump current value step period:

0:0.25 us

1:0.5 us

2:1 us

3:4 us

The charge pump current to stop at after the current is stepped down from START_CHP_CURRENT after VCO calibration is complete. The current is stepped down periodically with intervals as defined in CHP_STEP_PERIOD.

The charge pump current to start with after VCO calibration is complete. The current is then stepped down periodically to the value STOP_CHP_CURRENT with intervals as defined in

CHP_STEP_PERIOD.

Also used for overriding the charge pump current when CHP_CURRENT_OE=’1’

RXBPFTST (0x2B) - Receiver Bandpass Filters Test Register

Bit	Field Name	Reset	R/W
15	-	0	W0
14	RXBPF_CAP_OE	0	R/W
13:7	RXBPF_CAP_O[6:0]	0	R/W
6:0	RXBPF_CAP_RES[6:0]	0	R

Description

Reserved, write as 0.

RX bandpass filter capacitance calibration override enable.

RX bandpass filter capacitance calibration override value.

RX bandpass filter capacitance calibration result.

0:Minimum capacitance in the feedback.

1:Second smallest capacitance setting.

…

127:Maximum capacitance in the feedback.

FSMSTATE (0x2C) - Finite state machine information

Bit	Field Name	Reset	R/W
15:6	-	0	W0
5:0	FSM_CUR_STATE[5:0]	0	R

Description

Reserved, write as 0.

Provides the current state of the FIFO and Frame Control (FFCTRL) finite state machine. See the Radio control state machine section on page 43 for details.

SWRS041B

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Contents Key Features ApplicationsProduct Description Table of contents RF Data Buffering Ordering Information General Information Abbreviations ITU-TReferences Features Parameter Min Max Units Condition Absolute Maximum RatingsOperating Conditions Parameter Min Typ Max Units ConditionTransmit Section Electrical SpecificationsOverall Parameter Min Typ Max Unit Condition / NoteReceive Section Rssi / Carrier Sense If SectionFrequency Synthesizer Section Digital Inputs/Outputs VDDBattery Monitor Power SupplyVoltage Regulator CC2420 Pin Assignment Pin Pin Name Pin type Pin DescriptionAvddadc CC2420 simplified block diagram Circuit DescriptionCC2420 Input / output matching Power supply decoupling and filteringApplication Circuit Bias resistorOverview of external components DescriptionTransceiver Transceiver Bill of materials for the application circuits Symbol Chip sequence C0, C1, C2, … , C31 Ieee 802.15.4 Modulation FormatConfiguration Overview PhaseEvaluation Software SmartRF Studio user interface13 4-wire Serial Configuration and Data Interface Pin configurationRegister access SPI timing specification Status byte Parameter Symbol Min Max Units ConditionsRAM access Configuration registers write and read operations via SPI CC2420 RAM Memory Space Fifo access Multiple SPI accessAddress Byte Ordering Name Description Configuration interface Microcontroller Interface and Pin DescriptionReceive mode Rxfifo overflowPin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Demodulator Simplified Block Diagram Frame FormatTransmitted Synchronisation Header Length field MAC protocol data unitFormat of the Frame Control Field FCF Frame check sequence Buffered transmit mode Buffered receive modeRF Data Buffering Unbuffered, serial mode FifopAddress Recognition Acknowledge FramesAcknowledge frame format Radio control state machine Radio control states Nonce / counter MAC Security Operations Encryption and AuthenticationKeys Ieee 802.15.4 NonceCC2420 Security Flag Byte Stand-alone encryption In-line security operationsCTR mode encryption / decryption CBC-MAC21.7 CCM Rssi / Energy Detection Linear if and AGC SettingsMode LMIC Time TimingLink Quality Indication ValueRF Level dBm Clear Channel Assessment Frequency and Channel ProgrammingVoltage Regulator Output Power ProgrammingVCO and PLL Self-Calibration 27.1 VCOBattery Monitor Voltage regulator, simplified schematicCrystal Oscillator Crystal oscillator component values Input / Output MatchingTransmitter Test Modes Unmodulated carrierCC2420 Modulated spectrum plot System Considerations and Guidelines Battery operated systems Low-cost systemsBER / PER measurements PCB Layout Recommendations Antenna ConsiderationsCC2420 Configuration Registers Address Register Register type DescriptionConfiguration registers overview SaesBit Field Name Reset Main 0x10 Main Control RegisterXOSC16MBYPASS MDMCTRL0 0x11 Modem Control Register Reservedframemode Pancoordinator AdrdecodeCCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength CORRTHR40 Demodavgmode Modulationmode MDMCTRL1 0x12- Modem Control RegisterRssi 0x13 Rssi and CCA Status and Control Register RSSIVAL70Syncword 0x14 Sync Word Txctrl 0x15 Transmit Control RegisterRXCTRL0 0x16 Receive control register RXMIXBUFCUR10RXCTRL1 0x17 Receive control register Fsctrl 0x18 Frequency Synthesizer Control and Status Caldone Calrunning Locklength LockstatusSECCTRL0 0x19 Security Control Register SECMODE10Sectxl Secrxl Battmon 0x1B Battery Monitor Control registerSECCTRL1 0x1A Security Control Register Battmonok Battmonen BattmonvoltageManfidl 0x1E Manufacturer ID, Lower 16 Bit IOCFG0 0x1C I/O Configuration RegisterIOCFG1 0x1D I/O Configuration Register HSSDSRC20 SFDMUX40 CCAMUX40Manfidh 0x1F Manufacturer ID, Upper 16 Bit Fsmtc 0x20 Finite state machine time constantsManand 0x21 Manual signal and override register1 Isused = is * Isandmask + IsormaskVgagainoe Manor 0x22 Manual signal or override registerAgcctrl 0x23 AGC Control LnamixgainmodeoAGCTST0 0x24 AGC Test Register AGCTST1 0x25 AGC Test RegisterAGCTST2 0x26 AGC Test Register FSTST0 0x27 Frequency Synthesizer Test Register FSTST1 0x28 Frequency Synthesizer Test RegisterFSTST2 0x29 Frequency Synthesizer Test Register FSTST3 0x2A Frequency Synthesizer Test Register Rxbpftst 0x2B Receiver Bandpass Filters Test RegisterFsmstate 0x2C Finite state machine information Adcclockdisable Adctst 0x2D ADC Test RegisterDactst 0x2E DAC Test Register Txfifo 0x3E Transmit Fifo Byte register Oscillator must be running for accessing the RxfifoToptst 0x2F Top Level Test Register Rxfifo 0x3F Receive Fifo Byte registerTest Output Signals CCA test signal select tableSignal output on CCA pin Description SFD test signal select table Signal output on SFD pin DescriptionPackage Description QLP Quad Leadless Package QLPSoldering information Recommended layout for package QLPPackage thermal properties Thermal resistanceTube Specification 40.3 Plastic tube specification40.4 Carrier tape and reel specification Tape and Reel SpecificationGeneral Information 42.1 Document HistoryRevision Date Description/Changes Data Sheet Identification Product Status Definition Product Status DefinitionsAddress Information TI Worldwide Technical Support InternetProduct Information Centers 2007, Texas Instruments. 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