Texas Instruments 3138 155 232931 manual Frame Format, Demodulator Simplified Block Diagram

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I / Q Analog

IF signal

CC2420

ADC

 

 

Digital

 

 

 

Frequency

 

 

 

Digital

 

 

Symbol

 

 

Data

 

 

IF Channel

 

 

 

Offset

 

 

 

Data

 

 

Correlators and

 

 

Symbol

 

 

 

Filtering

 

 

 

Compensation

 

 

 

Filtering

 

 

Synchronisation

 

 

Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Average

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RSSI

 

 

RSSI

 

 

 

 

Correlation

 

 

 

 

 

 

 

 

Generator

 

 

 

 

 

 

 

 

Value (may be

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

used for LQI)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 16. Demodulator Simplified Block Diagram

16 Frame Format

CC2420 has hardware support for parts of the IEEE 802.15.4 frame format. This section gives a brief summary to the IEEE

802.15.4frame format, and describes how CC2420 is set up to comply with this.

Figure 17 [1] shows a schematic view of the IEEE 802.15.4 frame format. Similar figures describing specific frame formats

(data frames, beacon frames, acknowledgment frames and MAC command frames) are included in [1].

 

 

 

 

Bytes: 2

1

 

0 to 20

n

2

MAC

 

 

 

Frame

Data

 

Address

 

 

Frame Check

 

 

 

Control Field

Sequence

 

 

Frame payload

Sequence

Layer

 

 

 

 

Information

 

 

 

 

(FCF)

Number

 

 

 

(FCS)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAC Header (MHR)

 

 

MAC Payload

MAC Footer

 

 

 

 

 

 

 

 

 

 

 

(MFR)

Bytes:

4

1

1

 

 

 

5 + (0 to 20) + n

 

 

PHY

 

Preamble

Start of frame

Frame

 

 

 

MAC Protocol

 

 

 

Delimiter

 

 

 

Data Unit

 

 

Layer

 

Sequence

Length

 

 

 

 

 

 

(SFD)

 

 

 

(MPDU)

 

 

 

 

Synchronisation

Header

PHY Header

 

 

 

PHY Service Data Unit

 

 

 

(SHR)

 

(PHR)

 

 

 

(PSDU)

 

 

 

 

 

 

 

11 + (0 to 20) + n

 

 

 

 

 

 

 

 

 

PHY Protocol Data Unit

 

 

 

 

 

 

 

 

 

 

(PPDU)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 17. Schematic view of the IEEE 802.15.4 Frame Format [1]

16.1 Synchronisation header

The synchronisation header (SHR) consists of the preamble sequence followed by the start of frame delimiter (SFD). In [1], the preamble sequence is defined to be 4 bytes of 0x00. The SFD is one byte, set to 0xA7.

In CC2420, the preamble length and SFD is configurable. The default values are compliant with [1]. Changing these values will make the system non-compliant to IEEE 802.15.4.

A synchronisation header is always transmitted first in all transmit modes.

The preamble sequence length can be set by MDMCTRL0.PREAMBLE_LENGTH, while the SFD is programmed in the SYNCWORD register. SYNCWORD is 2 bytes long, which gives the user some extra flexibility as described below. Figure 18 shows how the CC2420 synchronisation header relates to the IEEE 802.15.4 specification.

The programmable preamble length only applies to transmission, it does not affect receive mode. The preamble length should not be set shorter than the default value. Note that 2 of the 8 zero-symbols in the preamble sequence required by [1] are included in the SYNCWORD register so that the CC2420 preamble sequence is only 6 symbols long for compliance with [1]. Two

SWRS041B

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Contents Key Features ApplicationsProduct Description Table of contents RF Data Buffering Ordering Information General Information Abbreviations ITU-TReferences Features Absolute Maximum Ratings Operating ConditionsParameter Min Max Units Condition Parameter Min Typ Max Units ConditionElectrical Specifications OverallTransmit Section Parameter Min Typ Max Unit Condition / NoteReceive Section Rssi / Carrier Sense If SectionFrequency Synthesizer Section Digital Inputs/Outputs VDDBattery Monitor Power SupplyVoltage Regulator CC2420 Pin Assignment Pin Pin Name Pin type Pin DescriptionAvddadc CC2420 simplified block diagram Circuit DescriptionCC2420 Power supply decoupling and filtering Application CircuitInput / output matching Bias resistorOverview of external components DescriptionTransceiver Transceiver Bill of materials for the application circuits Symbol Chip sequence C0, C1, C2, … , C31 Ieee 802.15.4 Modulation FormatConfiguration Overview PhaseEvaluation Software SmartRF Studio user interface13 4-wire Serial Configuration and Data Interface Pin configurationRegister access SPI timing specification Status byte Parameter Symbol Min Max Units ConditionsRAM access Configuration registers write and read operations via SPI CC2420 RAM Memory Space Fifo access Multiple SPI accessAddress Byte Ordering Name Description Configuration interface Microcontroller Interface and Pin Description Receive mode Rxfifo overflowPin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Demodulator Simplified Block Diagram Frame FormatTransmitted Synchronisation Header Length field MAC protocol data unitFormat of the Frame Control Field FCF Frame check sequence Buffered transmit mode Buffered receive modeRF Data Buffering Unbuffered, serial mode FifopAddress Recognition Acknowledge FramesAcknowledge frame format Radio control state machine Radio control states MAC Security Operations Encryption and Authentication KeysNonce / counter Ieee 802.15.4 NonceCC2420 Security Flag Byte Stand-alone encryption In-line security operationsCTR mode encryption / decryption CBC-MAC21.7 CCM Linear if and AGC Settings Mode LMIC TimeRssi / Energy Detection TimingLink Quality Indication ValueRF Level dBm Clear Channel Assessment Frequency and Channel ProgrammingOutput Power Programming VCO and PLL Self-CalibrationVoltage Regulator 27.1 VCOBattery Monitor Voltage regulator, simplified schematicCrystal Oscillator Input / Output Matching Transmitter Test ModesCrystal oscillator component values Unmodulated carrierCC2420 Modulated spectrum plot System Considerations and Guidelines Battery operated systems Low-cost systemsBER / PER measurements PCB Layout Recommendations Antenna ConsiderationsCC2420 Configuration Registers Address Register Register type DescriptionConfiguration registers overview SaesBit Field Name Reset Main 0x10 Main Control RegisterXOSC16MBYPASS MDMCTRL0 0x11 Modem Control Register Reservedframemode Pancoordinator AdrdecodeCCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength MDMCTRL1 0x12- Modem Control Register Rssi 0x13 Rssi and CCA Status and Control RegisterCORRTHR40 Demodavgmode Modulationmode RSSIVAL70Syncword 0x14 Sync Word Txctrl 0x15 Transmit Control RegisterRXCTRL0 0x16 Receive control register RXMIXBUFCUR10RXCTRL1 0x17 Receive control register Fsctrl 0x18 Frequency Synthesizer Control and Status Caldone Calrunning Locklength LockstatusSECCTRL0 0x19 Security Control Register SECMODE10Battmon 0x1B Battery Monitor Control register SECCTRL1 0x1A Security Control RegisterSectxl Secrxl Battmonok Battmonen BattmonvoltageIOCFG0 0x1C I/O Configuration Register IOCFG1 0x1D I/O Configuration RegisterManfidl 0x1E Manufacturer ID, Lower 16 Bit HSSDSRC20 SFDMUX40 CCAMUX40Manfidh 0x1F Manufacturer ID, Upper 16 Bit Fsmtc 0x20 Finite state machine time constantsManand 0x21 Manual signal and override register1 Isused = is * Isandmask + IsormaskManor 0x22 Manual signal or override register Agcctrl 0x23 AGC ControlVgagainoe LnamixgainmodeoAGCTST0 0x24 AGC Test Register AGCTST1 0x25 AGC Test RegisterAGCTST2 0x26 AGC Test Register FSTST0 0x27 Frequency Synthesizer Test Register FSTST1 0x28 Frequency Synthesizer Test RegisterFSTST2 0x29 Frequency Synthesizer Test Register FSTST3 0x2A Frequency Synthesizer Test Register Rxbpftst 0x2B Receiver Bandpass Filters Test RegisterFsmstate 0x2C Finite state machine information Adcclockdisable Adctst 0x2D ADC Test RegisterDactst 0x2E DAC Test Register Oscillator must be running for accessing the Rxfifo Toptst 0x2F Top Level Test RegisterTxfifo 0x3E Transmit Fifo Byte register Rxfifo 0x3F Receive Fifo Byte registerTest Output Signals CCA test signal select tableSignal output on CCA pin Description SFD test signal select table Signal output on SFD pin DescriptionPackage Description QLP Quad Leadless Package QLPRecommended layout for package QLP Package thermal propertiesSoldering information Thermal resistance40.3 Plastic tube specification 40.4 Carrier tape and reel specificationTube Specification Tape and Reel SpecificationGeneral Information 42.1 Document HistoryRevision Date Description/Changes Data Sheet Identification Product Status Definition Product Status DefinitionsAddress Information TI Worldwide Technical Support InternetProduct Information Centers 2007, Texas Instruments. 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