Texas Instruments 3138 155 232931 Clear Channel Assessment, Frequency and Channel Programming

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25 Clear Channel Assessment

The clear channel assessment signal is based on the measured RSSI value and a programmable threshold. The clear channel assessment function is used to implement the CSMA-CA functionality specified in [1]. CCA is valid when the receiver has been enabled for at least 8 symbol periods.

Carrier sense threshold level is programmed by RSSI.CCA_THR. The threshold value can be programmed in steps of 1 dB. A CCA hysteresis can also

be programmed in the MDMCTRL0.CCA_HYST control bits.

All 3 CCA modes specified by [1] are implemented in CC2420. They are set in MDMCTRL0.CCA_MODE, as can be seen in the register description. The different modes are:

CC2420

0Reserved

1Clear channel when received energy is below threshold.

2Clear channel when not receiving valid IEEE 802.15.4 data.

3Clear channel when energy is below threshold and not receiving valid IEEE 802.15.4 data

Clear channel assessment is available on the CCA output pin. CCA is active high, but the polarity may be changed by setting the IOCFG0.CCA_POLARITY control bit.

Implementing CSMA-CA may easiest be done by using the STXONCCA command strobe, as described in the Radio control state machine section on page 43. Transmission will then only start if the channel is clear. The TX_ACTIVE status bit (see Table 5) may be used to detect the result of the CCA.

26 Frequency and Channel Programming

The operating frequency is set by programming the 10 bit frequency word located in FSCTRL.FREQ[9:0]. The operating frequency FC in MHz is given by:

FC = 2048 + FSCTRL.FREQ[9:0] MHz

The frequency can be programmed with 1 MHz resolution. In receive mode the actual LO frequency is FC – 2 MHz, since a 2 MHz IF is used. Direct conversion is used for transmission, so here the LO frequency equals FC. The 2 MHz IF is automatically set by CC2420, so the frequency programming is equal for RX and TX.

IEEE 802.15.4 specifies 16 channels within the 2.4 GHz band, in 5 MHz steps, numbered 11 through 26. The RF frequency of channel k is given by [1]:

FC = 2405 + 5 (k-11) MHz, k=11, 12, ..., 26

For operation in channel k, the FSCTRL.FREQ register should therefore be set to:

FSCTRL.FREQ = 357 + 5 (k-11)

SWRS041B

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Contents Product Description Key FeaturesApplications Table of contents RF Data Buffering Ordering Information General Information Abbreviations ITU-TReferences Features Parameter Min Max Units Condition Absolute Maximum RatingsOperating Conditions Parameter Min Typ Max Units ConditionTransmit Section Electrical SpecificationsOverall Parameter Min Typ Max Unit Condition / NoteReceive Section Frequency Synthesizer Section Rssi / Carrier SenseIf Section Digital Inputs/Outputs VDDVoltage Regulator Battery MonitorPower Supply CC2420 Pin Assignment Pin Pin Name Pin type Pin DescriptionAvddadc CC2420 simplified block diagram Circuit DescriptionCC2420 Input / output matching Power supply decoupling and filteringApplication Circuit Bias resistorOverview of external components DescriptionTransceiver Transceiver Bill of materials for the application circuits Symbol Chip sequence C0, C1, C2, … , C31 Ieee 802.15.4 Modulation FormatConfiguration Overview PhaseEvaluation Software SmartRF Studio user interfaceRegister access 13 4-wire Serial Configuration and Data InterfacePin configuration SPI timing specification Status byte Parameter Symbol Min Max Units ConditionsRAM access Configuration registers write and read operations via SPI Address Byte Ordering Name Description CC2420 RAM Memory Space Fifo accessMultiple SPI access Configuration interface Microcontroller Interface and Pin DescriptionReceive mode Rxfifo overflowPin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Demodulator Simplified Block Diagram Frame FormatTransmitted Synchronisation Header Length field MAC protocol data unitFormat of the Frame Control Field FCF Frame check sequence RF Data Buffering Buffered transmit modeBuffered receive mode Unbuffered, serial mode FifopAddress Recognition Acknowledge FramesAcknowledge frame format Radio control state machine Radio control states Nonce / counter MAC Security Operations Encryption and AuthenticationKeys Ieee 802.15.4 NonceCC2420 Security Flag Byte Stand-alone encryption In-line security operations21.7 CCM CTR mode encryption / decryptionCBC-MAC Rssi / Energy Detection Linear if and AGC SettingsMode LMIC Time TimingRF Level dBm Link Quality IndicationValue Clear Channel Assessment Frequency and Channel ProgrammingVoltage Regulator Output Power ProgrammingVCO and PLL Self-Calibration 27.1 VCOBattery Monitor Voltage regulator, simplified schematicCrystal Oscillator Crystal oscillator component values Input / Output MatchingTransmitter Test Modes Unmodulated carrierCC2420 Modulated spectrum plot System Considerations and Guidelines BER / PER measurements Battery operated systemsLow-cost systems PCB Layout Recommendations Antenna ConsiderationsCC2420 Configuration Registers Address Register Register type DescriptionConfiguration registers overview SaesXOSC16MBYPASS Bit Field Name ResetMain 0x10 Main Control Register CCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength MDMCTRL0 0x11 Modem Control RegisterReservedframemode Pancoordinator Adrdecode CORRTHR40 Demodavgmode Modulationmode MDMCTRL1 0x12- Modem Control RegisterRssi 0x13 Rssi and CCA Status and Control Register RSSIVAL70Syncword 0x14 Sync Word Txctrl 0x15 Transmit Control RegisterRXCTRL0 0x16 Receive control register RXMIXBUFCUR10RXCTRL1 0x17 Receive control register Fsctrl 0x18 Frequency Synthesizer Control and Status Caldone Calrunning Locklength LockstatusSECCTRL0 0x19 Security Control Register SECMODE10Sectxl Secrxl Battmon 0x1B Battery Monitor Control registerSECCTRL1 0x1A Security Control Register Battmonok Battmonen BattmonvoltageManfidl 0x1E Manufacturer ID, Lower 16 Bit IOCFG0 0x1C I/O Configuration RegisterIOCFG1 0x1D I/O Configuration Register HSSDSRC20 SFDMUX40 CCAMUX40Manfidh 0x1F Manufacturer ID, Upper 16 Bit Fsmtc 0x20 Finite state machine time constantsManand 0x21 Manual signal and override register1 Isused = is * Isandmask + IsormaskVgagainoe Manor 0x22 Manual signal or override registerAgcctrl 0x23 AGC Control LnamixgainmodeoAGCTST2 0x26 AGC Test Register AGCTST0 0x24 AGC Test RegisterAGCTST1 0x25 AGC Test Register FSTST2 0x29 Frequency Synthesizer Test Register FSTST0 0x27 Frequency Synthesizer Test RegisterFSTST1 0x28 Frequency Synthesizer Test Register Fsmstate 0x2C Finite state machine information FSTST3 0x2A Frequency Synthesizer Test RegisterRxbpftst 0x2B Receiver Bandpass Filters Test Register Dactst 0x2E DAC Test Register AdcclockdisableAdctst 0x2D ADC Test Register Txfifo 0x3E Transmit Fifo Byte register Oscillator must be running for accessing the RxfifoToptst 0x2F Top Level Test Register Rxfifo 0x3F Receive Fifo Byte registerSignal output on CCA pin Description Test Output SignalsCCA test signal select table SFD test signal select table Signal output on SFD pin DescriptionPackage Description QLP Quad Leadless Package QLPSoldering information Recommended layout for package QLPPackage thermal properties Thermal resistanceTube Specification 40.3 Plastic tube specification40.4 Carrier tape and reel specification Tape and Reel SpecificationRevision Date Description/Changes General Information42.1 Document History Data Sheet Identification Product Status Definition Product Status DefinitionsProduct Information Centers Address InformationTI Worldwide Technical Support Internet 2007, Texas Instruments. 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