Texas Instruments 3138 155 232931 manual 13 4-wire Serial Configuration and Data Interface

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CC2420

13 4-wire Serial Configuration and Data Interface

CC2420 is configured via a simple 4-wire SPI-compatible interface (pins SI, SO, SCLK and CSn) where CC2420 is the slave. This interface is also used to read and write buffered data (see page 39). All address and data transfer on the SPI interface is done most significant bit first.

13.1 Pin configuration

The digital inputs SCLK, SI and CSn are high-impedance inputs (no internal pull- up) and should have external pull-ups if not driven. SO is high-impedance when CSn is high. An external pull-up should be used at SO to prevent floating input at microcontroller. Unused I/O pins on the MCU can be set to outputs with a fixed ‘0’ level to avoid leakage currents.

13.2 Register access

There are 33 16-bit configuration and status registers, 15 command strobe registers, and two 8-bit registers to access the separate transmit and receive FIFOs. Each of the 50 registers is addressed by a 6-bit address. The RAM/Register bit (bit 7) must be cleared for register access. The Read/Write bit (bit 6) selects a read or a write operation and makes up the 8-bit address field together with the 6-bit address.

In each register read or write cycle, 24 bits are sent on the SI-line. The CSn pin (Chip Select, active low) must be kept low during this transfer. The bit to be sent first is the

RAM/Register bit (set to 0 for register access), followed by the R/W bit (0 for write, 1 for read). The following 6 bits are the address-bits (A5:0). A5 is the most significant bit of the address and is sent first. The 16 data-bits are then transferred (D15:0), also MSB first. See Figure 9 for an illustration.

The configuration registers can also be read by the microcontroller via the same configuration interface. The R/W bit must be set high to initiate the data read-back. CC2420 then returns the data from the addressed register on the 16 clock cycles following the register address. The SO pin is used as the data output and must be configured as an input by the microcontroller.

The timing for the programming is also shown in Figure 9 with reference to Table

4.The clocking of the data on SI into the CC2420 is done on the positive edge of SCLK. When the last bit, D0, of the 16 data-bits has been written, the data word is loaded in the internal configuration register.

Multiple registers may be written without releasing CSn, as described in the Multiple SPI access section on page 31.

The register data will be retained during power down mode, but not when the power-supply is turned off (e.g. by disabling the voltage regulator using the VREG_EN pin). The registers can be programmed in any order.

SWRS041B

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Contents Key Features ApplicationsProduct Description Table of contents RF Data Buffering Ordering Information General Information ITU-T AbbreviationsReferences Features Parameter Min Typ Max Units Condition Absolute Maximum RatingsOperating Conditions Parameter Min Max Units ConditionParameter Min Typ Max Unit Condition / Note Electrical SpecificationsOverall Transmit SectionReceive Section Rssi / Carrier Sense If SectionFrequency Synthesizer Section VDD Digital Inputs/OutputsBattery Monitor Power SupplyVoltage Regulator CC2420 Pin Pin Name Pin type Pin Description Pin AssignmentAvddadc Circuit Description CC2420 simplified block diagramCC2420 Bias resistor Power supply decoupling and filteringApplication Circuit Input / output matchingDescription Overview of external componentsTransceiver Transceiver Bill of materials for the application circuits Ieee 802.15.4 Modulation Format Symbol Chip sequence C0, C1, C2, … , C31Phase Configuration OverviewSmartRF Studio user interface Evaluation Software13 4-wire Serial Configuration and Data Interface Pin configurationRegister access Parameter Symbol Min Max Units Conditions SPI timing specification Status byteRAM access Configuration registers write and read operations via SPI CC2420 RAM Memory Space Fifo access Multiple SPI accessAddress Byte Ordering Name Description Microcontroller Interface and Pin Description Configuration interfaceRxfifo overflow Receive modePin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Frame Format Demodulator Simplified Block DiagramMAC protocol data unit Transmitted Synchronisation Header Length fieldFormat of the Frame Control Field FCF Frame check sequence Buffered transmit mode Buffered receive modeRF Data Buffering Fifop Unbuffered, serial modeAcknowledge Frames Address RecognitionAcknowledge frame format Radio control state machine Radio control states Ieee 802.15.4 Nonce MAC Security Operations Encryption and AuthenticationKeys Nonce / counterIn-line security operations CC2420 Security Flag Byte Stand-alone encryptionCTR mode encryption / decryption CBC-MAC21.7 CCM Timing Linear if and AGC SettingsMode LMIC Time Rssi / Energy DetectionLink Quality Indication ValueRF Level dBm Frequency and Channel Programming Clear Channel Assessment27.1 VCO Output Power ProgrammingVCO and PLL Self-Calibration Voltage RegulatorVoltage regulator, simplified schematic Battery MonitorCrystal Oscillator Unmodulated carrier Input / Output MatchingTransmitter Test Modes Crystal oscillator component valuesCC2420 Modulated spectrum plot System Considerations and Guidelines Battery operated systems Low-cost systemsBER / PER measurements Antenna Considerations PCB Layout RecommendationsCC2420 Address Register Register type Description Configuration RegistersSaes Configuration registers overviewBit Field Name Reset Main 0x10 Main Control RegisterXOSC16MBYPASS MDMCTRL0 0x11 Modem Control Register Reservedframemode Pancoordinator AdrdecodeCCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength RSSIVAL70 MDMCTRL1 0x12- Modem Control RegisterRssi 0x13 Rssi and CCA Status and Control Register CORRTHR40 Demodavgmode ModulationmodeTxctrl 0x15 Transmit Control Register Syncword 0x14 Sync WordRXMIXBUFCUR10 RXCTRL0 0x16 Receive control registerRXCTRL1 0x17 Receive control register Caldone Calrunning Locklength Lockstatus Fsctrl 0x18 Frequency Synthesizer Control and StatusSECMODE10 SECCTRL0 0x19 Security Control RegisterBattmonok Battmonen Battmonvoltage Battmon 0x1B Battery Monitor Control registerSECCTRL1 0x1A Security Control Register Sectxl SecrxlHSSDSRC20 SFDMUX40 CCAMUX40 IOCFG0 0x1C I/O Configuration RegisterIOCFG1 0x1D I/O Configuration Register Manfidl 0x1E Manufacturer ID, Lower 16 BitFsmtc 0x20 Finite state machine time constants Manfidh 0x1F Manufacturer ID, Upper 16 BitIsused = is * Isandmask + Isormask Manand 0x21 Manual signal and override register1Lnamixgainmodeo Manor 0x22 Manual signal or override registerAgcctrl 0x23 AGC Control VgagainoeAGCTST0 0x24 AGC Test Register AGCTST1 0x25 AGC Test RegisterAGCTST2 0x26 AGC Test Register FSTST0 0x27 Frequency Synthesizer Test Register FSTST1 0x28 Frequency Synthesizer Test RegisterFSTST2 0x29 Frequency Synthesizer Test Register FSTST3 0x2A Frequency Synthesizer Test Register Rxbpftst 0x2B Receiver Bandpass Filters Test RegisterFsmstate 0x2C Finite state machine information Adcclockdisable Adctst 0x2D ADC Test RegisterDactst 0x2E DAC Test Register Rxfifo 0x3F Receive Fifo Byte register Oscillator must be running for accessing the RxfifoToptst 0x2F Top Level Test Register Txfifo 0x3E Transmit Fifo Byte registerTest Output Signals CCA test signal select tableSignal output on CCA pin Description Signal output on SFD pin Description SFD test signal select tableQuad Leadless Package QLP Package Description QLPThermal resistance Recommended layout for package QLPPackage thermal properties Soldering informationTape and Reel Specification 40.3 Plastic tube specification40.4 Carrier tape and reel specification Tube SpecificationGeneral Information 42.1 Document HistoryRevision Date Description/Changes Product Status Definitions Data Sheet Identification Product Status DefinitionAddress Information TI Worldwide Technical Support InternetProduct Information Centers 2007, Texas Instruments. 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