Texas Instruments 3138 155 232931 manual IOCFG0 0x1C I/O Configuration Register, PARTNUM30

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CC2420

IOCFG0 (0x1C) – I/O Configuration Register 0

	Bit	Field Name	Reset	R/W
	15:12	-	0	W0
	11	BCN_ACCEPT	0	R/W

10	FIFO_POLARITY	0	R/W

9	FIFOP_POLARITY	0	R/W

8	SFD_POLARITY	0	R/W

7	CCA_POLARITY	0	R/W

6:0	FIFOP_THR[6:0]	64	R/W

Description

Reserved, write as 0

Accept all beacon frames when address recognition is enabled. This bit should be set when the PAN identifier programmed into CC2420 RAM is equal to 0xFFFF and cleared otherwise. This bit is don't care when MDMCTRL0.ADR_DECODE = 0.

0 : Only accept beacons with a source PAN identifier which matches the PAN identifier programmed into CC2420 RAM

1 : Accept all beacons regardless of the source PAN identifier

Polarity of the output signal FIFO.

0 : Polarity is active high

1 : Polarity is active low

Polarity of the output signal FIFOP.

0 : Polarity is active high

1 : Polarity is active low

Polarity of the SFD pin.

0 : Polarity is active high

1 : Polarity is active low

Polarity of the CCA pin.

0 : Polarity is active high

1 : Polarity is active low

FIFOP_THR sets the threshold in number of bytes in the RXFIFO for FIFOP to go active.

IOCFG1 (0x1D) – I/O Configuration Register 1

Bit	Field Name	Reset	R/W
15:13	-	0	W0
12:10	HSSD_SRC[2:0]	0	R/W

9:5	SFDMUX[4:0]	0	R/W
4:0	CCAMUX[4:0]	0	R/W

Description

Reserved, write as 0

The HSSD module is used as follows:

0:Off.

1:Output AGC status (gain setting / peak detector status / accumulator value)

2:Output ADC I and Q values.

3:Output I/Q after digital down mix and channel filtering.

4:Reserved

5:Reserved

6:Input ADC I and Q values

7:Input DAC I and Q values.

The HSSD module requires that the FS is up and running as it uses CLK_PRE (~150 MHZ) to produce its ~37.5 MHz data clock and serialize its output words.

Multiplexer setting for the SFD pin.

Multiplexer setting for the CCA pin.

MANFIDL (0x1E) - Manufacturer ID, Lower 16 Bit

Bit	Field Name	Reset	R/W
15:12	PARTNUM[3:0]	2	R
11:0	MANFID[11:0]	0x33D	R

Description

The device part number. CC2420 has part number 0x002.

Gives the JEDEC manufacturer ID. The actual manufacturer ID can be found in MANIFID[7:1], the number of continuation bytes in MANFID[11:8] and MANFID[0]=1.

Chipcon's JEDEC manufacturer ID is 0x7F 0x7F 0x7F 0x9E (0x1E preceded by three continuation bytes.)

SWRS041B

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Contents Key Features ApplicationsProduct Description Table of contents RF Data Buffering Ordering Information General Information Abbreviations ITU-TReferences Features Absolute Maximum Ratings Operating ConditionsParameter Min Max Units Condition Parameter Min Typ Max Units ConditionElectrical Specifications OverallTransmit Section Parameter Min Typ Max Unit Condition / NoteReceive Section Rssi / Carrier Sense If SectionFrequency Synthesizer Section Digital Inputs/Outputs VDDBattery Monitor Power SupplyVoltage Regulator CC2420 Pin Assignment Pin Pin Name Pin type Pin DescriptionAvddadc CC2420 simplified block diagram Circuit DescriptionCC2420 Power supply decoupling and filtering Application CircuitInput / output matching Bias resistorOverview of external components DescriptionTransceiver Transceiver Bill of materials for the application circuits Symbol Chip sequence C0, C1, C2, … , C31 Ieee 802.15.4 Modulation FormatConfiguration Overview PhaseEvaluation Software SmartRF Studio user interface13 4-wire Serial Configuration and Data Interface Pin configurationRegister access SPI timing specification Status byte Parameter Symbol Min Max Units ConditionsRAM access Configuration registers write and read operations via SPI CC2420 RAM Memory Space Fifo access Multiple SPI accessAddress Byte Ordering Name Description Configuration interface Microcontroller Interface and Pin DescriptionReceive mode Rxfifo overflowPin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Demodulator Simplified Block Diagram Frame FormatTransmitted Synchronisation Header Length field MAC protocol data unitFormat of the Frame Control Field FCF Frame check sequence Buffered transmit mode Buffered receive modeRF Data Buffering Unbuffered, serial mode FifopAddress Recognition Acknowledge FramesAcknowledge frame format Radio control state machine Radio control states MAC Security Operations Encryption and Authentication KeysNonce / counter Ieee 802.15.4 NonceCC2420 Security Flag Byte Stand-alone encryption In-line security operationsCTR mode encryption / decryption CBC-MAC21.7 CCM Linear if and AGC Settings Mode LMIC TimeRssi / Energy Detection TimingLink Quality Indication ValueRF Level dBm Clear Channel Assessment Frequency and Channel ProgrammingOutput Power Programming VCO and PLL Self-CalibrationVoltage Regulator 27.1 VCOBattery Monitor Voltage regulator, simplified schematicCrystal Oscillator Input / Output Matching Transmitter Test ModesCrystal oscillator component values Unmodulated carrierCC2420 Modulated spectrum plot System Considerations and Guidelines Battery operated systems Low-cost systemsBER / PER measurements PCB Layout Recommendations Antenna ConsiderationsCC2420 Configuration Registers Address Register Register type DescriptionConfiguration registers overview SaesBit Field Name Reset Main 0x10 Main Control RegisterXOSC16MBYPASS MDMCTRL0 0x11 Modem Control Register Reservedframemode Pancoordinator AdrdecodeCCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength MDMCTRL1 0x12- Modem Control Register Rssi 0x13 Rssi and CCA Status and Control RegisterCORRTHR40 Demodavgmode Modulationmode RSSIVAL70Syncword 0x14 Sync Word Txctrl 0x15 Transmit Control RegisterRXCTRL0 0x16 Receive control register RXMIXBUFCUR10RXCTRL1 0x17 Receive control register Fsctrl 0x18 Frequency Synthesizer Control and Status Caldone Calrunning Locklength LockstatusSECCTRL0 0x19 Security Control Register SECMODE10Battmon 0x1B Battery Monitor Control register SECCTRL1 0x1A Security Control RegisterSectxl Secrxl Battmonok Battmonen BattmonvoltageIOCFG0 0x1C I/O Configuration Register IOCFG1 0x1D I/O Configuration RegisterManfidl 0x1E Manufacturer ID, Lower 16 Bit HSSDSRC20 SFDMUX40 CCAMUX40Manfidh 0x1F Manufacturer ID, Upper 16 Bit Fsmtc 0x20 Finite state machine time constantsManand 0x21 Manual signal and override register1 Isused = is * Isandmask + IsormaskManor 0x22 Manual signal or override register Agcctrl 0x23 AGC ControlVgagainoe LnamixgainmodeoAGCTST0 0x24 AGC Test Register AGCTST1 0x25 AGC Test RegisterAGCTST2 0x26 AGC Test Register FSTST0 0x27 Frequency Synthesizer Test Register FSTST1 0x28 Frequency Synthesizer Test RegisterFSTST2 0x29 Frequency Synthesizer Test Register FSTST3 0x2A Frequency Synthesizer Test Register Rxbpftst 0x2B Receiver Bandpass Filters Test RegisterFsmstate 0x2C Finite state machine information Adcclockdisable Adctst 0x2D ADC Test RegisterDactst 0x2E DAC Test Register Oscillator must be running for accessing the Rxfifo Toptst 0x2F Top Level Test RegisterTxfifo 0x3E Transmit Fifo Byte register Rxfifo 0x3F Receive Fifo Byte registerTest Output Signals CCA test signal select tableSignal output on CCA pin Description SFD test signal select table Signal output on SFD pin DescriptionPackage Description QLP Quad Leadless Package QLPRecommended layout for package QLP Package thermal propertiesSoldering information Thermal resistance40.3 Plastic tube specification 40.4 Carrier tape and reel specificationTube Specification Tape and Reel SpecificationGeneral Information 42.1 Document HistoryRevision Date Description/Changes Data Sheet Identification Product Status Definition Product Status DefinitionsAddress Information TI Worldwide Technical Support InternetProduct Information Centers 2007, Texas Instruments. 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