Texas Instruments 3138 155 232931 manual Package Description QLP, Quad Leadless Package QLP

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CC2420

39 Package Description (QLP 48)

Note: The figure is an illustration only and not to scale.

Quad Leadless Package (QLP)

		D	D1	E	E1	e	b	L	D2	E2

QLP 48	Min	6.9	6.65	6.9	6.65		0.18	0.3	5.05	5.05
		7.0	6.75	7.0	6.75	0.5		0.4	5.10	5.10
	Max	7.1	6.85	7.1	6.85		0.30	0.5	5.15	5.15

The overall packet height is 0.85 +/- 0.05

All dimensions in mm

The package is compliant to JEDEC standard MO-220.

SWRS041B

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Image 83

Contents Product Description Key FeaturesApplications Table of contents RF Data Buffering Ordering Information General Information ITU-T AbbreviationsReferences Features Parameter Min Typ Max Units Condition Absolute Maximum RatingsOperating Conditions Parameter Min Max Units ConditionParameter Min Typ Max Unit Condition / Note Electrical SpecificationsOverall Transmit SectionReceive Section Frequency Synthesizer Section Rssi / Carrier SenseIf Section VDD Digital Inputs/OutputsVoltage Regulator Battery MonitorPower Supply CC2420 Pin Pin Name Pin type Pin Description Pin AssignmentAvddadc Circuit Description CC2420 simplified block diagramCC2420 Bias resistor Power supply decoupling and filteringApplication Circuit Input / output matchingDescription Overview of external componentsTransceiver Transceiver Bill of materials for the application circuits Ieee 802.15.4 Modulation Format Symbol Chip sequence C0, C1, C2, … , C31Phase Configuration OverviewSmartRF Studio user interface Evaluation SoftwareRegister access 13 4-wire Serial Configuration and Data InterfacePin configuration Parameter Symbol Min Max Units Conditions SPI timing specification Status byteRAM access Configuration registers write and read operations via SPI Address Byte Ordering Name Description CC2420 RAM Memory Space Fifo accessMultiple SPI access Microcontroller Interface and Pin Description Configuration interfaceRxfifo overflow Receive modePin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Frame Format Demodulator Simplified Block DiagramMAC protocol data unit Transmitted Synchronisation Header Length fieldFormat of the Frame Control Field FCF Frame check sequence RF Data Buffering Buffered transmit modeBuffered receive mode Fifop Unbuffered, serial modeAcknowledge Frames Address RecognitionAcknowledge frame format Radio control state machine Radio control states Ieee 802.15.4 Nonce MAC Security Operations Encryption and AuthenticationKeys Nonce / counterIn-line security operations CC2420 Security Flag Byte Stand-alone encryption21.7 CCM CTR mode encryption / decryptionCBC-MAC Timing Linear if and AGC SettingsMode LMIC Time Rssi / Energy DetectionRF Level dBm Link Quality IndicationValue Frequency and Channel Programming Clear Channel Assessment27.1 VCO Output Power ProgrammingVCO and PLL Self-Calibration Voltage RegulatorVoltage regulator, simplified schematic Battery MonitorCrystal Oscillator Unmodulated carrier Input / Output MatchingTransmitter Test Modes Crystal oscillator component valuesCC2420 Modulated spectrum plot System Considerations and Guidelines BER / PER measurements Battery operated systemsLow-cost systems Antenna Considerations PCB Layout RecommendationsCC2420 Address Register Register type Description Configuration RegistersSaes Configuration registers overviewXOSC16MBYPASS Bit Field Name ResetMain 0x10 Main Control Register CCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength MDMCTRL0 0x11 Modem Control RegisterReservedframemode Pancoordinator Adrdecode RSSIVAL70 MDMCTRL1 0x12- Modem Control RegisterRssi 0x13 Rssi and CCA Status and Control Register CORRTHR40 Demodavgmode ModulationmodeTxctrl 0x15 Transmit Control Register Syncword 0x14 Sync WordRXMIXBUFCUR10 RXCTRL0 0x16 Receive control registerRXCTRL1 0x17 Receive control register Caldone Calrunning Locklength Lockstatus Fsctrl 0x18 Frequency Synthesizer Control and StatusSECMODE10 SECCTRL0 0x19 Security Control RegisterBattmonok Battmonen Battmonvoltage Battmon 0x1B Battery Monitor Control registerSECCTRL1 0x1A Security Control Register Sectxl SecrxlHSSDSRC20 SFDMUX40 CCAMUX40 IOCFG0 0x1C I/O Configuration RegisterIOCFG1 0x1D I/O Configuration Register Manfidl 0x1E Manufacturer ID, Lower 16 BitFsmtc 0x20 Finite state machine time constants Manfidh 0x1F Manufacturer ID, Upper 16 BitIsused = is * Isandmask + Isormask Manand 0x21 Manual signal and override register1Lnamixgainmodeo Manor 0x22 Manual signal or override registerAgcctrl 0x23 AGC Control VgagainoeAGCTST2 0x26 AGC Test Register AGCTST0 0x24 AGC Test RegisterAGCTST1 0x25 AGC Test Register FSTST2 0x29 Frequency Synthesizer Test Register FSTST0 0x27 Frequency Synthesizer Test RegisterFSTST1 0x28 Frequency Synthesizer Test Register Fsmstate 0x2C Finite state machine information FSTST3 0x2A Frequency Synthesizer Test RegisterRxbpftst 0x2B Receiver Bandpass Filters Test Register Dactst 0x2E DAC Test Register AdcclockdisableAdctst 0x2D ADC Test Register Rxfifo 0x3F Receive Fifo Byte register Oscillator must be running for accessing the RxfifoToptst 0x2F Top Level Test Register Txfifo 0x3E Transmit Fifo Byte registerSignal output on CCA pin Description Test Output SignalsCCA test signal select table Signal output on SFD pin Description SFD test signal select tableQuad Leadless Package QLP Package Description QLPThermal resistance Recommended layout for package QLPPackage thermal properties Soldering informationTape and Reel Specification 40.3 Plastic tube specification40.4 Carrier tape and reel specification Tube SpecificationRevision Date Description/Changes General Information42.1 Document History Product Status Definitions Data Sheet Identification Product Status DefinitionProduct Information Centers Address InformationTI Worldwide Technical Support Internet 2007, Texas Instruments. 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