Texas Instruments 3138 155 232931 manual General Information, Document History

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			CC2420
42	General Information
42.1	Document History

Revision		Date	Description/Changes
SWRS041b		2007-03-19 Slightly changed optimum load impedance on Page 9 and 19 to better describe the
			Application circuit.

SWRS041a		2006-12-18	Updated ordering information.
			Updated address information.
			Typical data latency changed from 2 to 3 us.
			Updates reflecting the programmable polarity of FIFO, FIFOP, SFD and CCA pins.
			Clarification relating to VREG_EN as digital input.
			BATT_OK changed to BATTMON_OK for consistency.
			MANFIDH.VERSION register, reset value changed to ”current version is 3”.
			Added reset values for several registers.
			Some typographical changes.
			Removed Chipcon specific Disclaimer, Trademarks and Life Support Policy sections.

SWRS041		2006-04-06 Ordering part number changed from CC2420-RTB2 and CC2420-RTR2 to CC2420Z-
(1.4)			RTB1 and CC2420Z-RTR1 respectively.
(1.4)

1.32005-10-03 Important: New recommended setting for RXBPF_LOCUR in RXCTRL1 (0x17) use 1 instead of reset value 0.

Updated address information.

Added new balun circuit with transmission lines in section Application Circuit. Updated electrical specifications with measured data on CC2420 EM with new balun. Updated values and figure for suggested application circuit with folded dipole antenna.

Corrected values for capacitors in Table 2, discrete balun. Added data latency figure in receiver specification. Updated crystal oscillator start up time.

Updated PLL loop filter bandwidth. Updated adjacent channel rejection figures. Updated current consumption for RX mode. Typographical errors corrected in text and figures.

Removed comment about tuning capacitor for crystal oscillator. Added statement that RAM access shall not be used for FIFO access. Added more details about RSSI.

Clarified the interpretation of a programmed synchronisation word. Updated purchasing information.

Updated soldering standard.

Added chapter numbering and split table for electrical specifications for readability. Gathered and added information related to pin configurations in section 13. Included TX_UNDERFLOW and RX_UNDERFLOW in state diagram.

Disclaimer updated to include Z-stack TM information. Product status changed to “Full Production”.

SWRS041B

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Contents Product Description Key FeaturesApplications Table of contents RF Data Buffering Ordering Information General Information Abbreviations ITU-TReferences Features Parameter Min Max Units Condition Absolute Maximum RatingsOperating Conditions Parameter Min Typ Max Units ConditionTransmit Section Electrical SpecificationsOverall Parameter Min Typ Max Unit Condition / NoteReceive Section Frequency Synthesizer Section Rssi / Carrier SenseIf Section Digital Inputs/Outputs VDDVoltage Regulator Battery MonitorPower Supply CC2420 Pin Assignment Pin Pin Name Pin type Pin DescriptionAvddadc CC2420 simplified block diagram Circuit DescriptionCC2420 Input / output matching Power supply decoupling and filteringApplication Circuit Bias resistorOverview of external components DescriptionTransceiver Transceiver Bill of materials for the application circuits Symbol Chip sequence C0, C1, C2, … , C31 Ieee 802.15.4 Modulation FormatConfiguration Overview PhaseEvaluation Software SmartRF Studio user interfaceRegister access 13 4-wire Serial Configuration and Data InterfacePin configuration SPI timing specification Status byte Parameter Symbol Min Max Units ConditionsRAM access Configuration registers write and read operations via SPI Address Byte Ordering Name Description CC2420 RAM Memory Space Fifo accessMultiple SPI access Configuration interface Microcontroller Interface and Pin DescriptionReceive mode Rxfifo overflowPin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Demodulator Simplified Block Diagram Frame FormatTransmitted Synchronisation Header Length field MAC protocol data unitFormat of the Frame Control Field FCF Frame check sequence RF Data Buffering Buffered transmit modeBuffered receive mode Unbuffered, serial mode FifopAddress Recognition Acknowledge FramesAcknowledge frame format Radio control state machine Radio control states Nonce / counter MAC Security Operations Encryption and AuthenticationKeys Ieee 802.15.4 NonceCC2420 Security Flag Byte Stand-alone encryption In-line security operations21.7 CCM CTR mode encryption / decryptionCBC-MAC Rssi / Energy Detection Linear if and AGC SettingsMode LMIC Time TimingRF Level dBm Link Quality IndicationValue Clear Channel Assessment Frequency and Channel ProgrammingVoltage Regulator Output Power ProgrammingVCO and PLL Self-Calibration 27.1 VCOBattery Monitor Voltage regulator, simplified schematicCrystal Oscillator Crystal oscillator component values Input / Output MatchingTransmitter Test Modes Unmodulated carrierCC2420 Modulated spectrum plot System Considerations and Guidelines BER / PER measurements Battery operated systemsLow-cost systems PCB Layout Recommendations Antenna ConsiderationsCC2420 Configuration Registers Address Register Register type DescriptionConfiguration registers overview SaesXOSC16MBYPASS Bit Field Name ResetMain 0x10 Main Control Register CCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength MDMCTRL0 0x11 Modem Control RegisterReservedframemode Pancoordinator Adrdecode CORRTHR40 Demodavgmode Modulationmode MDMCTRL1 0x12- Modem Control RegisterRssi 0x13 Rssi and CCA Status and Control Register RSSIVAL70Syncword 0x14 Sync Word Txctrl 0x15 Transmit Control RegisterRXCTRL0 0x16 Receive control register RXMIXBUFCUR10RXCTRL1 0x17 Receive control register Fsctrl 0x18 Frequency Synthesizer Control and Status Caldone Calrunning Locklength LockstatusSECCTRL0 0x19 Security Control Register SECMODE10Sectxl Secrxl Battmon 0x1B Battery Monitor Control registerSECCTRL1 0x1A Security Control Register Battmonok Battmonen BattmonvoltageManfidl 0x1E Manufacturer ID, Lower 16 Bit IOCFG0 0x1C I/O Configuration RegisterIOCFG1 0x1D I/O Configuration Register HSSDSRC20 SFDMUX40 CCAMUX40Manfidh 0x1F Manufacturer ID, Upper 16 Bit Fsmtc 0x20 Finite state machine time constantsManand 0x21 Manual signal and override register1 Isused = is * Isandmask + IsormaskVgagainoe Manor 0x22 Manual signal or override registerAgcctrl 0x23 AGC Control LnamixgainmodeoAGCTST2 0x26 AGC Test Register AGCTST0 0x24 AGC Test RegisterAGCTST1 0x25 AGC Test Register FSTST2 0x29 Frequency Synthesizer Test Register FSTST0 0x27 Frequency Synthesizer Test RegisterFSTST1 0x28 Frequency Synthesizer Test Register Fsmstate 0x2C Finite state machine information FSTST3 0x2A Frequency Synthesizer Test RegisterRxbpftst 0x2B Receiver Bandpass Filters Test Register Dactst 0x2E DAC Test Register AdcclockdisableAdctst 0x2D ADC Test Register Txfifo 0x3E Transmit Fifo Byte register Oscillator must be running for accessing the RxfifoToptst 0x2F Top Level Test Register Rxfifo 0x3F Receive Fifo Byte registerSignal output on CCA pin Description Test Output SignalsCCA test signal select table SFD test signal select table Signal output on SFD pin DescriptionPackage Description QLP Quad Leadless Package QLPSoldering information Recommended layout for package QLPPackage thermal properties Thermal resistanceTube Specification 40.3 Plastic tube specification40.4 Carrier tape and reel specification Tape and Reel SpecificationRevision Date Description/Changes General Information42.1 Document History Data Sheet Identification Product Status Definition Product Status DefinitionsProduct Information Centers Address InformationTI Worldwide Technical Support Internet 2007, Texas Instruments. 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