Texas Instruments 3138 155 232931 manual Circuit Description, CC2420 simplified block diagram

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CC2420

8 Circuit Description

LNA

TX/RX CONTROL

AUTOMATIC GAIN CONTROL

ADC

ADC

DIGITAL

DEMODULATOR

-Digital RSSI

-Gain Control

-Image Suppression

-Channel Filtering

-Demodulation

-Frame synchronization

Serial

voltage

regulator

SmartRF →

CC2420

Power

Control

PA

Σ

XOSC

On-chip

BIAS

R

16 MHz

0

90

FREQ

SYNTH

TX POWER CONTROL

DAC

DAC

LOGIC

INTERFACE

 

DIGITAL

CONTROL

WITH FIFO

BUFFERS,

 

CRC AND

 

ENCRYPTION

 

 

DIGITAL

MODULATOR

- Data spreading - Modulation

Serial microcontroller interface

Digital and Analog test interface

Figure 2. CC2420 simplified block diagram

A simplified block diagram of CC2420 is shown in Figure 2.

CC2420 features a low-IF receiver. The received RF signal is amplified by the low- noise amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF (2 MHz), the complex I/Q signal is filtered and amplified, and then digitized by the ADCs. Automatic gain control, final channel filtering, de- spreading, symbol correlation and byte synchronisation are performed digitally.

When the SFD pin goes active, this indicates that a start of frame delimiter has been detected. CC2420 buffers the received data in a 128 byte receive FIFO. The user may read the FIFO through an SPI interface. CRC is verified in hardware. RSSI and correlation values are appended to the frame. CCA is available on a pin in receive mode. Serial (unbuffered) data modes are also available for test purposes.

The CC2420 transmitter is based on direct up-conversion. The data is buffered in a 128 byte transmit FIFO (separate from the receive FIFO). The preamble and start of frame delimiter are generated by hardware. Each symbol (4 bits) is spread using the IEEE 802.15.4 spreading sequence to 32 chips and output to the digital-to-analog converters (DACs).

An analog low pass filter passes the signal to the quadrature (I and Q) upconversion mixers. The RF signal is amplified in the power amplifier (PA) and fed to the antenna.

The internal T/R switch circuitry makes the antenna interface and matching easy. The RF connection is differential. A balun may be used for single-ended antennas. The biasing of the PA and LNA is done by connecting TXRX_SWITCH to RF_P and RF_N through an external DC path.

The frequency synthesizer includes a completely on-chip LC VCO and a 90 degrees phase splitter for generating the I

SWRS041B

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Contents Product Description Key FeaturesApplications Table of contents RF Data Buffering Ordering Information General Information ITU-T AbbreviationsReferences Features Operating Conditions Absolute Maximum RatingsParameter Min Max Units Condition Parameter Min Typ Max Units ConditionOverall Electrical SpecificationsTransmit Section Parameter Min Typ Max Unit Condition / NoteReceive Section Frequency Synthesizer Section Rssi / Carrier SenseIf Section VDD Digital Inputs/OutputsVoltage Regulator Battery MonitorPower Supply CC2420 Pin Pin Name Pin type Pin Description Pin AssignmentAvddadc Circuit Description CC2420 simplified block diagramCC2420 Application Circuit Power supply decoupling and filteringInput / output matching Bias resistorDescription Overview of external componentsTransceiver Transceiver Bill of materials for the application circuits Ieee 802.15.4 Modulation Format Symbol Chip sequence C0, C1, C2, … , C31Phase Configuration OverviewSmartRF Studio user interface Evaluation SoftwareRegister access 13 4-wire Serial Configuration and Data InterfacePin configuration Parameter Symbol Min Max Units Conditions SPI timing specification Status byteRAM access Configuration registers write and read operations via SPI Address Byte Ordering Name Description CC2420 RAM Memory Space Fifo accessMultiple SPI access Microcontroller Interface and Pin Description Configuration interfaceRxfifo overflow Receive modePin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Frame Format Demodulator Simplified Block DiagramMAC protocol data unit Transmitted Synchronisation Header Length fieldFormat of the Frame Control Field FCF Frame check sequence RF Data Buffering Buffered transmit modeBuffered receive mode Fifop Unbuffered, serial modeAcknowledge Frames Address RecognitionAcknowledge frame format Radio control state machine Radio control states Keys MAC Security Operations Encryption and AuthenticationNonce / counter Ieee 802.15.4 NonceIn-line security operations CC2420 Security Flag Byte Stand-alone encryption21.7 CCM CTR mode encryption / decryptionCBC-MAC Mode LMIC Time Linear if and AGC SettingsRssi / Energy Detection TimingRF Level dBm Link Quality IndicationValue Frequency and Channel Programming Clear Channel AssessmentVCO and PLL Self-Calibration Output Power ProgrammingVoltage Regulator 27.1 VCOVoltage regulator, simplified schematic Battery MonitorCrystal Oscillator Transmitter Test Modes Input / Output MatchingCrystal oscillator component values Unmodulated carrierCC2420 Modulated spectrum plot System Considerations and Guidelines BER / PER measurements Battery operated systemsLow-cost systems Antenna Considerations PCB Layout RecommendationsCC2420 Address Register Register type Description Configuration RegistersSaes Configuration registers overviewXOSC16MBYPASS Bit Field Name ResetMain 0x10 Main Control Register CCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength MDMCTRL0 0x11 Modem Control RegisterReservedframemode Pancoordinator Adrdecode Rssi 0x13 Rssi and CCA Status and Control Register MDMCTRL1 0x12- Modem Control RegisterCORRTHR40 Demodavgmode Modulationmode RSSIVAL70Txctrl 0x15 Transmit Control Register Syncword 0x14 Sync WordRXMIXBUFCUR10 RXCTRL0 0x16 Receive control registerRXCTRL1 0x17 Receive control register Caldone Calrunning Locklength Lockstatus Fsctrl 0x18 Frequency Synthesizer Control and StatusSECMODE10 SECCTRL0 0x19 Security Control RegisterSECCTRL1 0x1A Security Control Register Battmon 0x1B Battery Monitor Control registerSectxl Secrxl Battmonok Battmonen BattmonvoltageIOCFG1 0x1D I/O Configuration Register IOCFG0 0x1C I/O Configuration RegisterManfidl 0x1E Manufacturer ID, Lower 16 Bit HSSDSRC20 SFDMUX40 CCAMUX40Fsmtc 0x20 Finite state machine time constants Manfidh 0x1F Manufacturer ID, Upper 16 BitIsused = is * Isandmask + Isormask Manand 0x21 Manual signal and override register1Agcctrl 0x23 AGC Control Manor 0x22 Manual signal or override registerVgagainoe LnamixgainmodeoAGCTST2 0x26 AGC Test Register AGCTST0 0x24 AGC Test RegisterAGCTST1 0x25 AGC Test Register FSTST2 0x29 Frequency Synthesizer Test Register FSTST0 0x27 Frequency Synthesizer Test RegisterFSTST1 0x28 Frequency Synthesizer Test Register Fsmstate 0x2C Finite state machine information FSTST3 0x2A Frequency Synthesizer Test RegisterRxbpftst 0x2B Receiver Bandpass Filters Test Register Dactst 0x2E DAC Test Register AdcclockdisableAdctst 0x2D ADC Test Register Toptst 0x2F Top Level Test Register Oscillator must be running for accessing the RxfifoTxfifo 0x3E Transmit Fifo Byte register Rxfifo 0x3F Receive Fifo Byte registerSignal output on CCA pin Description Test Output SignalsCCA test signal select table Signal output on SFD pin Description SFD test signal select tableQuad Leadless Package QLP Package Description QLPPackage thermal properties Recommended layout for package QLPSoldering information Thermal resistance40.4 Carrier tape and reel specification 40.3 Plastic tube specificationTube Specification Tape and Reel SpecificationRevision Date Description/Changes General Information42.1 Document History Product Status Definitions Data Sheet Identification Product Status DefinitionProduct Information Centers Address InformationTI Worldwide Technical Support Internet 2007, Texas Instruments. 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