Texas Instruments 3138 155 232931 manual SPI timing specification Status byte

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CC2420

tsp	tch	tcl	tsd	thd	t	ns
						ns

SCLK

CSn

Write to register / RXFIFO:

SI SO

0	0	A5	A4	A3	A2	A1	A0	X DW15 DW14 DW13 DW12 DW11 DW10 DW9 DW8 X DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0	X
S7	S6	S5	S4	S3	S2	S1	S0	X

Write to TXFIFO:

SI

0

0

A5

A4

A3

A2

A1

A0

X DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0 X DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0

X

SO

S7

S6

S5

S4

S3

S2

S1

S0

S7

S6

S5

S4

S3

S2

S1

S0

S7

S6

S5

S4

S3

S2

S1

S0

S7

Read from register / RXFIFO:

SI

SO

SI

SO

SI

SO

0

1

A5

A4

A3

A2

A1

A0

X

S7

S6

S5

S4

S3

S2

S1

S0

DR15

DR14 DR13 DR12 DR11 DR10 DR9 DR8

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

DR15

Read and write one byte to RAM: (multiple read / writes

also possible)

1

A6

A5

A4

A3

A2

A1

A0

X B1

B0

0

X

X

X

X

X X DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0

X

S7

S6

S5

S4

S3

S2

S1

S0

X

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

DR7

Read one byte from RAM: (multiple reads also possible)

1

A6

A5

A4

A3

A2

A1

A0

X

B1

B0

1

X

X

X

X

X

X

S7

S6

S5

S4

S3

S2

S1

S0

X

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

DR7

Figure 9. SPI timing diagram

Parameter	Symbol	Min	Max	Units	Conditions

SCLK, clock	FSCLK		10	MHz
frequency

SCLK low	tcl	25		ns	The minimum time SCLK must be low.
pulse
duration

SCLK high	tch	25		ns	The minimum time SCLK must be high.
pulse
duration

CSn setup	tsp	25		ns	The minimum time CSn must be low before the first
time					positive edge of SCLK.

CSn hold time	tns	25		ns	The minimum time CSn must be held low after the
					last negative edge of SCLK.
SI setup time	tsd	25		ns	The minimum time data on SI must be ready
					before the positive edge of SCLK.

SI hold time	thd	25		ns	The minimum time data must be held at SI, after
					the positive edge of SCLK.
Rise time	trise		100	ns	The maximum rise time for SCLK and CSn
Fall time	tfall		100	ns	The maximum fall time for SCLK and CSn

Note: The set-up- and hold-times refer to 50% of VDD.

Table 4. SPI timing specification

13.3 Status byte

During transfer of the register access byte, command strobes, the first RAM address byte and data transfer to the TXFIFO, the CC2420 status byte is returned on the SO pin. The status byte contains 6 status bits which are described in Table 5.

Issuing a SNOP (no operation) command strobe may be used to read the status byte. It may also be read during access to chip functions such as register or FIFO access.

SWRS041B

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Contents Applications Key FeaturesProduct Description Table of contents RF Data Buffering Ordering Information General Information Abbreviations ITU-TReferences Features Absolute Maximum Ratings Operating ConditionsParameter Min Max Units Condition Parameter Min Typ Max Units ConditionElectrical Specifications OverallTransmit Section Parameter Min Typ Max Unit Condition / NoteReceive Section If Section Rssi / Carrier SenseFrequency Synthesizer Section Digital Inputs/Outputs VDDPower Supply Battery MonitorVoltage Regulator CC2420 Pin Assignment Pin Pin Name Pin type Pin DescriptionAvddadc CC2420 simplified block diagram Circuit DescriptionCC2420 Power supply decoupling and filtering Application CircuitInput / output matching Bias resistorOverview of external components DescriptionTransceiver Transceiver Bill of materials for the application circuits Symbol Chip sequence C0, C1, C2, … , C31 Ieee 802.15.4 Modulation FormatConfiguration Overview PhaseEvaluation Software SmartRF Studio user interfacePin configuration 13 4-wire Serial Configuration and Data InterfaceRegister access SPI timing specification Status byte Parameter Symbol Min Max Units ConditionsRAM access Configuration registers write and read operations via SPI Multiple SPI access CC2420 RAM Memory Space Fifo accessAddress Byte Ordering Name Description Configuration interface Microcontroller Interface and Pin DescriptionReceive mode Rxfifo overflowPin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Demodulator Simplified Block Diagram Frame FormatTransmitted Synchronisation Header Length field MAC protocol data unitFormat of the Frame Control Field FCF Frame check sequence Buffered receive mode Buffered transmit modeRF Data Buffering Unbuffered, serial mode FifopAddress Recognition Acknowledge FramesAcknowledge frame format Radio control state machine Radio control states MAC Security Operations Encryption and Authentication KeysNonce / counter Ieee 802.15.4 NonceCC2420 Security Flag Byte Stand-alone encryption In-line security operationsCBC-MAC CTR mode encryption / decryption21.7 CCM Linear if and AGC Settings Mode LMIC TimeRssi / Energy Detection TimingValue Link Quality IndicationRF Level dBm Clear Channel Assessment Frequency and Channel ProgrammingOutput Power Programming VCO and PLL Self-CalibrationVoltage Regulator 27.1 VCOBattery Monitor Voltage regulator, simplified schematicCrystal Oscillator Input / Output Matching Transmitter Test ModesCrystal oscillator component values Unmodulated carrierCC2420 Modulated spectrum plot System Considerations and Guidelines Low-cost systems Battery operated systemsBER / PER measurements PCB Layout Recommendations Antenna ConsiderationsCC2420 Configuration Registers Address Register Register type DescriptionConfiguration registers overview SaesMain 0x10 Main Control Register Bit Field Name ResetXOSC16MBYPASS Reservedframemode Pancoordinator Adrdecode MDMCTRL0 0x11 Modem Control RegisterCCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength MDMCTRL1 0x12- Modem Control Register Rssi 0x13 Rssi and CCA Status and Control RegisterCORRTHR40 Demodavgmode Modulationmode RSSIVAL70Syncword 0x14 Sync Word Txctrl 0x15 Transmit Control RegisterRXCTRL0 0x16 Receive control register RXMIXBUFCUR10RXCTRL1 0x17 Receive control register Fsctrl 0x18 Frequency Synthesizer Control and Status Caldone Calrunning Locklength LockstatusSECCTRL0 0x19 Security Control Register SECMODE10Battmon 0x1B Battery Monitor Control register SECCTRL1 0x1A Security Control RegisterSectxl Secrxl Battmonok Battmonen BattmonvoltageIOCFG0 0x1C I/O Configuration Register IOCFG1 0x1D I/O Configuration RegisterManfidl 0x1E Manufacturer ID, Lower 16 Bit HSSDSRC20 SFDMUX40 CCAMUX40Manfidh 0x1F Manufacturer ID, Upper 16 Bit Fsmtc 0x20 Finite state machine time constantsManand 0x21 Manual signal and override register1 Isused = is * Isandmask + IsormaskManor 0x22 Manual signal or override register Agcctrl 0x23 AGC ControlVgagainoe LnamixgainmodeoAGCTST1 0x25 AGC Test Register AGCTST0 0x24 AGC Test RegisterAGCTST2 0x26 AGC Test Register FSTST1 0x28 Frequency Synthesizer Test Register FSTST0 0x27 Frequency Synthesizer Test RegisterFSTST2 0x29 Frequency Synthesizer Test Register Rxbpftst 0x2B Receiver Bandpass Filters Test Register FSTST3 0x2A Frequency Synthesizer Test RegisterFsmstate 0x2C Finite state machine information Adctst 0x2D ADC Test Register AdcclockdisableDactst 0x2E DAC Test Register Oscillator must be running for accessing the Rxfifo Toptst 0x2F Top Level Test RegisterTxfifo 0x3E Transmit Fifo Byte register Rxfifo 0x3F Receive Fifo Byte registerCCA test signal select table Test Output SignalsSignal output on CCA pin Description SFD test signal select table Signal output on SFD pin DescriptionPackage Description QLP Quad Leadless Package QLPRecommended layout for package QLP Package thermal propertiesSoldering information Thermal resistance40.3 Plastic tube specification 40.4 Carrier tape and reel specificationTube Specification Tape and Reel Specification42.1 Document History General InformationRevision Date Description/Changes Data Sheet Identification Product Status Definition Product Status DefinitionsTI Worldwide Technical Support Internet Address InformationProduct Information Centers 2007, Texas Instruments. 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