Texas Instruments 3138 155 232931 manual Manand 0x21 Manual signal and override register1

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CC2420

MANAND (0x21) - Manual signal AND override register1

 

Bit

Field Name

Reset

R/W

15

VGA_RESET_N

1

R/W

 

 

 

 

 

 

14

BIAS_PD

1

R/W

13

BALUN_CTRL

1

R/W

 

 

 

 

 

 

12

RXTX

1

R/W

 

 

 

 

 

 

11

PRE_PD

1

R/W

10

PA_N_PD

1

R/W

9

PA_P_PD

1

R/W

 

 

 

 

 

 

8

DAC_LPF_PD

1

R/W

7

XOSC16M_PD

1

R/W

6

RXBPF_CAL_PD

1

R/W

 

 

 

 

 

 

5

CHP_PD

1

R/W

4

FS_PD

1

R/W

3

ADC_PD

1

R/W

2

VGA_PD

1

R/W

1

RXBPF_PD

1

R/W

0

LNAMIX_PD

1

R/W

 

 

 

 

 

 

 

 

 

 

 

 

Description

The VGA_RESET_N signal is used to reset the peak detectors in the VGA in the RX chain.

Global bias power down (1)

The BALUN_CTRL signal controls whether the PA should receive its required external biasing (1) or not (0) by controlling the RX/TX output switch.

RXTX signal: controls whether the LO buffers (0) or PA buffers

(1)should be used. Powerdown of prescaler. Powerdown of PA (negative path).

Powerdown of PA (positive path). When PA_N_PD=1 and PA_P_PD=1 the up-conversion mixers are in powerdown.

Powerdown of TX DACs.

Powerdown control of complex bandpass receive filter calibration oscillator.

Powerdown control of charge pump.

Powerdown control of VCO, I/Q generator, LO buffers.

Powerdown control of the ADCs.

Powerdown control of the VGA.

Powerdown control of complex bandpass receive filter.

Powerdown control of LNA, down-conversion mixers and front- end bias.

1For some important signals the value used by analog and digital modules can be overridden manually. This is done as follows for the hypothetical important signal IS:

IS_USED = (IS * IS_AND_MASK) + IS_OR_MASK,

using boolean notation.

The AND-mask and OR-mask for the important signals listed resides in the MANAND and MANOR registers, respectively.

Examples:

•Writing 0xFFFE to MANAND and 0x0000 to MANOR will force LNAMIX_PD≡0 whereas all other signals will be unaffected.

•Writing 0xFFFF to MANAND and 0x0001 to MANOR will force LNAMIX_PD≡1 whereas all other signals will be unaffected.

SWRS041B

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Contents Product Description Key FeaturesApplications Table of contents RF Data Buffering Ordering Information General Information Abbreviations ITU-TReferences Features Parameter Min Max Units Condition Absolute Maximum RatingsOperating Conditions Parameter Min Typ Max Units ConditionTransmit Section Electrical SpecificationsOverall Parameter Min Typ Max Unit Condition / NoteReceive Section Frequency Synthesizer Section Rssi / Carrier SenseIf Section Digital Inputs/Outputs VDDVoltage Regulator Battery MonitorPower Supply CC2420 Pin Assignment Pin Pin Name Pin type Pin DescriptionAvddadc CC2420 simplified block diagram Circuit DescriptionCC2420 Input / output matching Power supply decoupling and filteringApplication Circuit Bias resistorOverview of external components DescriptionTransceiver Transceiver Bill of materials for the application circuits Symbol Chip sequence C0, C1, C2, … , C31 Ieee 802.15.4 Modulation FormatConfiguration Overview PhaseEvaluation Software SmartRF Studio user interfaceRegister access 13 4-wire Serial Configuration and Data InterfacePin configuration SPI timing specification Status byte Parameter Symbol Min Max Units ConditionsRAM access Configuration registers write and read operations via SPI Address Byte Ordering Name Description CC2420 RAM Memory Space Fifo accessMultiple SPI access Configuration interface Microcontroller Interface and Pin DescriptionReceive mode Rxfifo overflowPin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Demodulator Simplified Block Diagram Frame FormatTransmitted Synchronisation Header Length field MAC protocol data unitFormat of the Frame Control Field FCF Frame check sequence RF Data Buffering Buffered transmit modeBuffered receive mode Unbuffered, serial mode FifopAddress Recognition Acknowledge FramesAcknowledge frame format Radio control state machine Radio control states Nonce / counter MAC Security Operations Encryption and AuthenticationKeys Ieee 802.15.4 NonceCC2420 Security Flag Byte Stand-alone encryption In-line security operations21.7 CCM CTR mode encryption / decryptionCBC-MAC Rssi / Energy Detection Linear if and AGC SettingsMode LMIC Time TimingRF Level dBm Link Quality IndicationValue Clear Channel Assessment Frequency and Channel ProgrammingVoltage Regulator Output Power ProgrammingVCO and PLL Self-Calibration 27.1 VCOBattery Monitor Voltage regulator, simplified schematicCrystal Oscillator Crystal oscillator component values Input / Output MatchingTransmitter Test Modes Unmodulated carrierCC2420 Modulated spectrum plot System Considerations and Guidelines BER / PER measurements Battery operated systemsLow-cost systems PCB Layout Recommendations Antenna ConsiderationsCC2420 Configuration Registers Address Register Register type DescriptionConfiguration registers overview SaesXOSC16MBYPASS Bit Field Name ResetMain 0x10 Main Control Register CCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength MDMCTRL0 0x11 Modem Control RegisterReservedframemode Pancoordinator Adrdecode CORRTHR40 Demodavgmode Modulationmode MDMCTRL1 0x12- Modem Control RegisterRssi 0x13 Rssi and CCA Status and Control Register RSSIVAL70Syncword 0x14 Sync Word Txctrl 0x15 Transmit Control RegisterRXCTRL0 0x16 Receive control register RXMIXBUFCUR10RXCTRL1 0x17 Receive control register Fsctrl 0x18 Frequency Synthesizer Control and Status Caldone Calrunning Locklength LockstatusSECCTRL0 0x19 Security Control Register SECMODE10Sectxl Secrxl Battmon 0x1B Battery Monitor Control registerSECCTRL1 0x1A Security Control Register Battmonok Battmonen BattmonvoltageManfidl 0x1E Manufacturer ID, Lower 16 Bit IOCFG0 0x1C I/O Configuration RegisterIOCFG1 0x1D I/O Configuration Register HSSDSRC20 SFDMUX40 CCAMUX40Manfidh 0x1F Manufacturer ID, Upper 16 Bit Fsmtc 0x20 Finite state machine time constantsManand 0x21 Manual signal and override register1 Isused = is * Isandmask + IsormaskVgagainoe Manor 0x22 Manual signal or override registerAgcctrl 0x23 AGC Control LnamixgainmodeoAGCTST2 0x26 AGC Test Register AGCTST0 0x24 AGC Test RegisterAGCTST1 0x25 AGC Test Register FSTST2 0x29 Frequency Synthesizer Test Register FSTST0 0x27 Frequency Synthesizer Test RegisterFSTST1 0x28 Frequency Synthesizer Test Register Fsmstate 0x2C Finite state machine information FSTST3 0x2A Frequency Synthesizer Test RegisterRxbpftst 0x2B Receiver Bandpass Filters Test Register Dactst 0x2E DAC Test Register AdcclockdisableAdctst 0x2D ADC Test Register Txfifo 0x3E Transmit Fifo Byte register Oscillator must be running for accessing the RxfifoToptst 0x2F Top Level Test Register Rxfifo 0x3F Receive Fifo Byte registerSignal output on CCA pin Description Test Output SignalsCCA test signal select table SFD test signal select table Signal output on SFD pin DescriptionPackage Description QLP Quad Leadless Package QLPSoldering information Recommended layout for package QLPPackage thermal properties Thermal resistanceTube Specification 40.3 Plastic tube specification40.4 Carrier tape and reel specification Tape and Reel SpecificationRevision Date Description/Changes General Information42.1 Document History Data Sheet Identification Product Status Definition Product Status DefinitionsProduct Information Centers Address InformationTI Worldwide Technical Support Internet 2007, Texas Instruments. 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