Texas Instruments 3138 155 232931 manual Toptst 0x2F Top Level Test Register

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TOPTST (0x2F) - Top Level Test Register

Bit	Field Name	Reset	R/W
15:8	-	0	W0
7	RAM_BIST_RUN	0	R/W

6	TEST_BATTMON_EN	0	R/W
5	VC_IN_TEST_EN	0	R/W

4	ATESTMOD_PD	1	R/W

3:0	ATESTMOD_MODE[3:0]	0

CC2420

Description

Reserved, write as 0.

Enable BIST of the RAM

0 : RAM BIST disabled, normal operation

1 : RAM BIST Enabled. Result output to pin, as set in IOCFG1.

Enable test output of the battery monitor.

When ATESTMOD_MODE=7 this controls whether the ATEST2 in is used to output the VC node voltage (0) or to control the VC node voltage (1).

Powerdown of analog test module.

0 : Power up

1 : Power down

When ATESTMOD_PD=0, the function of the analog test module is as follows:

0:Outputs “I” (ATEST1) and “Q” (ATEST2) from RxMIX.

1:Inputs “I” (ATEST2) and “Q” (ATEST1) to BPF.

2:Outputs “I” (ATEST1) and “Q” (ATEST2) from VGA.

3:Inputs “I” (ATEST2) and “Q” (ATEST1) to ADC.

4:Outputs “I” (ATEST1) and “Q” (ATEST2) from LPF.

5:Inputs “I” (ATEST2) and “Q” (ATEST1) to TxMIX.

6:Outputs “P” (ATEST1) and “N” (ATEST2) from Prescaler. Must be terminated externally.

7:Connects TX IF to RX IF and simultaneously the ATEST1 pin to the internal VC node (see VC_IN_TEST_EN).

8.Connect ATEST1 (input) to ATEST2 (output) through single2diff and diff2single buffers, used for measurements on the test-interface

RESERVED (0x30) - Reserved register containing spare control and status bits

Bit	Field Name	Reset	R/W
15:0	RES[15:0]	0	R/W

Description

Reserved for future use

TXFIFO (0x3E) – Transmit FIFO Byte register

Bit	Field Name	Reset	R/W	Description
7:0	TXFIFO[7:0]	0	W	Transmit FIFO byte register, write only. Reading the TXFIFO is
				only possible using RAM read. Note that the crystal oscillator
				must be running for writing to the TXFIFO.

RXFIFO (0x3F) – Receive FIFO Byte register

Bit	Field Name	Reset	R/W	Description
7:0	RXFIFO[7:0]	0	R/W	Receive FIFO byte register, read / write. Note that the crystal
				oscillator must be running for accessing the RXFIFO.

SWRS041B

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Contents Product Description Key FeaturesApplications Table of contents RF Data Buffering Ordering Information General Information Abbreviations ITU-TReferences Features Absolute Maximum Ratings Operating ConditionsParameter Min Max Units Condition Parameter Min Typ Max Units ConditionElectrical Specifications OverallTransmit Section Parameter Min Typ Max Unit Condition / NoteReceive Section Frequency Synthesizer Section Rssi / Carrier SenseIf Section Digital Inputs/Outputs VDDVoltage Regulator Battery MonitorPower Supply CC2420 Pin Assignment Pin Pin Name Pin type Pin DescriptionAvddadc CC2420 simplified block diagram Circuit DescriptionCC2420 Power supply decoupling and filtering Application CircuitInput / output matching Bias resistorOverview of external components DescriptionTransceiver Transceiver Bill of materials for the application circuits Symbol Chip sequence C0, C1, C2, … , C31 Ieee 802.15.4 Modulation FormatConfiguration Overview PhaseEvaluation Software SmartRF Studio user interfaceRegister access 13 4-wire Serial Configuration and Data InterfacePin configuration SPI timing specification Status byte Parameter Symbol Min Max Units ConditionsRAM access Configuration registers write and read operations via SPI Address Byte Ordering Name Description CC2420 RAM Memory Space Fifo accessMultiple SPI access Configuration interface Microcontroller Interface and Pin DescriptionReceive mode Rxfifo overflowPin activity examples during receive Demodulator, Symbol Synchroniser and Data Decision Demodulator Simplified Block Diagram Frame FormatTransmitted Synchronisation Header Length field MAC protocol data unitFormat of the Frame Control Field FCF Frame check sequence RF Data Buffering Buffered transmit modeBuffered receive mode Unbuffered, serial mode FifopAddress Recognition Acknowledge FramesAcknowledge frame format Radio control state machine Radio control states MAC Security Operations Encryption and Authentication KeysNonce / counter Ieee 802.15.4 NonceCC2420 Security Flag Byte Stand-alone encryption In-line security operations21.7 CCM CTR mode encryption / decryptionCBC-MAC Linear if and AGC Settings Mode LMIC TimeRssi / Energy Detection TimingRF Level dBm Link Quality IndicationValue Clear Channel Assessment Frequency and Channel ProgrammingOutput Power Programming VCO and PLL Self-CalibrationVoltage Regulator 27.1 VCOBattery Monitor Voltage regulator, simplified schematicCrystal Oscillator Input / Output Matching Transmitter Test ModesCrystal oscillator component values Unmodulated carrierCC2420 Modulated spectrum plot System Considerations and Guidelines BER / PER measurements Battery operated systemsLow-cost systems PCB Layout Recommendations Antenna ConsiderationsCC2420 Configuration Registers Address Register Register type DescriptionConfiguration registers overview SaesXOSC16MBYPASS Bit Field Name ResetMain 0x10 Main Control Register CCAHYST20 CCAMODE10 Autocrc Autoack Preamblelength MDMCTRL0 0x11 Modem Control RegisterReservedframemode Pancoordinator Adrdecode MDMCTRL1 0x12- Modem Control Register Rssi 0x13 Rssi and CCA Status and Control RegisterCORRTHR40 Demodavgmode Modulationmode RSSIVAL70Syncword 0x14 Sync Word Txctrl 0x15 Transmit Control RegisterRXCTRL0 0x16 Receive control register RXMIXBUFCUR10RXCTRL1 0x17 Receive control register Fsctrl 0x18 Frequency Synthesizer Control and Status Caldone Calrunning Locklength LockstatusSECCTRL0 0x19 Security Control Register SECMODE10Battmon 0x1B Battery Monitor Control register SECCTRL1 0x1A Security Control RegisterSectxl Secrxl Battmonok Battmonen BattmonvoltageIOCFG0 0x1C I/O Configuration Register IOCFG1 0x1D I/O Configuration RegisterManfidl 0x1E Manufacturer ID, Lower 16 Bit HSSDSRC20 SFDMUX40 CCAMUX40Manfidh 0x1F Manufacturer ID, Upper 16 Bit Fsmtc 0x20 Finite state machine time constantsManand 0x21 Manual signal and override register1 Isused = is * Isandmask + IsormaskManor 0x22 Manual signal or override register Agcctrl 0x23 AGC ControlVgagainoe LnamixgainmodeoAGCTST2 0x26 AGC Test Register AGCTST0 0x24 AGC Test RegisterAGCTST1 0x25 AGC Test Register FSTST2 0x29 Frequency Synthesizer Test Register FSTST0 0x27 Frequency Synthesizer Test RegisterFSTST1 0x28 Frequency Synthesizer Test Register Fsmstate 0x2C Finite state machine information FSTST3 0x2A Frequency Synthesizer Test RegisterRxbpftst 0x2B Receiver Bandpass Filters Test Register Dactst 0x2E DAC Test Register AdcclockdisableAdctst 0x2D ADC Test Register Oscillator must be running for accessing the Rxfifo Toptst 0x2F Top Level Test RegisterTxfifo 0x3E Transmit Fifo Byte register Rxfifo 0x3F Receive Fifo Byte registerSignal output on CCA pin Description Test Output SignalsCCA test signal select table SFD test signal select table Signal output on SFD pin DescriptionPackage Description QLP Quad Leadless Package QLPRecommended layout for package QLP Package thermal propertiesSoldering information Thermal resistance40.3 Plastic tube specification 40.4 Carrier tape and reel specificationTube Specification Tape and Reel SpecificationRevision Date Description/Changes General Information42.1 Document History Data Sheet Identification Product Status Definition Product Status DefinitionsProduct Information Centers Address InformationTI Worldwide Technical Support Internet 2007, Texas Instruments. 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