Company X Accessories C1030-5510 manual Cypress FX-2 LP and USB basics, Clocking Fpga designs

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FPGA design

Cypress FX-2 LP and USB basics

Several data transfer types are defined in USB 2.0 specification. High-speed bulk transfer is the one and only mode of interest to end users. USB transfers are packet oriented and have a time framing scheme. USB packets consist of USB protocol and user payload data. Payload could have a variable length of up to 512 bytes per packet. Packet size is fixed to the maximum value of 512 bytes for data communication with CESYS USB cards to achieve highest possible data throughput. USB peripherals could have several logical channels to the host. The data source/sink for each channel inside the USB peripheral is called the USB endpoint. Each endpoint can be configured as “IN”- (channel direction: peripheral => host) or “OUT”-endpoint (channel direction: host => peripheral) from host side perspective. CESYS USB cards support two endpoints, one for each direction. FX-2 has an integrated USB SIE (Serial Interface Engine) handling USB protocol and transferring user payload data to the appropriate endpoint. So end users do not have to care about USB protocol in their own applications. FX-2 endpoints are realized as 2 kB buffers. These buffers can be accessed over a FIFO-like interface with a 16 bit tristate data bus by external hardware. External hardware acts as a master, polling FIFO flags, applying read- and write-strobes and transferring data. Therefore this FX-2 data transfer mechanism is called “slave FIFO mode”. As already mentioned, all data is transferred in multiples of 512 bytes. External hardware has to ensure, that the data written to IN-endpoint is aligned to this value, so that data will be transmitted from endpoint buffer to host. The 512 byte alignment normally causes no restrictions in data streaming applications with endless data transfers. Maybe it is necessary to fill up endpoint buffer with dummy data, if some kind of host timeout condition has to be met. Another FX-2 data transfer mechanism is called “GPIF (General Programmable InterFace) mode”. The GPIF engine inside the FX-2 acts as a master to endpoint buffers, transferring data and presenting configurable handshake waveforms to external hardware. CESYS USB card supports “slave FIFO mode” for data communication only. “GPIF mode” is exclusively used for downloading configuration bitstreams to FPGA.

Clocking FPGA designs

The 48 MHz SYSCLK oscillator is an onboard clock source for the FPGA. It is used as interface clock (IFCLK) between FX-2 slave FIFO bus and FPGA I/Os. So this clock source must be used for data transfers to and from FPGA over USB! Appropriate timing constraints can be found in “*.ucf”-files of design examples included in delivery.

It is strictly recommended to use a single clock domain whenever possible. Using a fully synchronous system architecture often results in smaller, less complex and more performant FPGA designs (compare XilinxTM white paper WP331 “Timing Closure/Coding Guidelines”).

USBS6 / C1030-5510

 

http://www.cesys.com/

User Doc V0.3

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preliminary

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Contents June 29 USBS6Copyright information Included in delivery Feature listSummary of USBS6 Spartan-6TMFPGA Block DiagramXC6SLX16-2CSG324C Fpga features USBS6 Top View Bus- powered USB is used as power supply input 3V@ ??? mA Powering USBS6Modes of operation ModeName ConfigurationJtag connector USB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A Signal NameUSB2.0 controller Lpddr Sdram MT46H64M16LFCK-5 External memoryMCB1DQ0 SPI Flash MX25L12845EMI-10G PeripheralsFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 HEX rotary DIP switchLEDs Direction Comment External expansion connectorsUSB to serial Uart interface J3 VG 96-pin external expansion connector J4 IDC 2x25-Pin external expansion connector IDC 2x25-Pin external expansion connector J4ADDIO16 Clocking Fpga designs Cypress FX-2 LP and USB basicsIntroduction to example Fpga designs FX-2/FPGA slave Fifo connectionISE Generate Programming File Properties Gen. Opt Fpga source code license Disclaimer of warrantyFpga source code copyright information Src/wishbonepkg.vhd Design usbs6socFiles and modules Src/wbintercon.vhd Src/usbs6soctop.vhdSrc/wbmafx2.vhd Src/wbslbram.vhdSrc/wbsluart.vhd Src/wbslmcb.vhdSrc/xiluartmacro Src/xilmcbmigSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by slaves Wishbone signals driven by the masterExample Design usbs6bramSrc/simtb/wbslbramtb.vhd Src/usbs6bramtop.vhdUsbs6bram.xise Usbs6bram.ucfWbslbramtb.cmd Changes to previous versions IntroductionWindows Driver installationRequirements Build UDKLets assume to use c\\udkapi Drivers LinuxPCI Makefile creation and build Preliminary Add project to UDK build Use APIs in own projects++ and .NET API API Error handlingAPI Functions in detail Error code Kind of error GetLastErrorCodeGetLastErrorText Methods/FunctionsDeInit Device enumerationInit DeviceType Description EnumerateGetDeviceCount Static unsigned int ceDeviceGetDeviceCountStatic ceDevice *ceDeviceGetDeviceunsigned int uiIdx GetDeviceGetUDKVersionString Information gatheringGetDeviceUID GetDeviceNameGetMaxTransferSize GetBusTypeConstant Bus Open Using devicesClose Void ceDeviceOpenWriteRegister ReadRegisterReadBlock WriteBlockWaitForInterrupt EnableInterruptResetFPGA ProgramFPGAFromBIN SetTimeOutProgramFPGAFromMemory ProgramFPGAFromMemoryZVoid ceDeviceEnableBurstbool bEnable EnableBurstIntroduction UDKLabUDKLab Main Screen Main screenDevice selection flow Using UDKLabPrepare to work with device Fpga configurationProjects Fpga design flashingSequence contents Add new initializing task Sequence start Content panelRegister panel Register entryData area panel Data area entryHow to store configuration data in SPI-Flash Using SPI-Flash for configurationM25P16 Fpga Connection Jtag Signal Name J3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT IO pairing and etch length reportNet name Direction52.506 Etch Length mm B18 Direction Fpga Bank Etch Length mm A28 J4 IDC-50 pin connector Differential pairs 17 IN/OUTAddio 42.990 USBS6 mechanical dimensions in mm Mechanical dimensionsTable of contents Table of Contents USB PCI ++ API
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