IO pairing and etch length report
J3 VG-96 pin connector - Differential pairs (28 IN, 12 IN/OUT )
PIN | Net name | FPGA IO | P / N | Direction | FPGA BANK | Etch Length (mm) |
A4 | VG96_IO0 | U2 | P | IN | BANK 3 | 62.370 |
B4 | VG96_IO1 | U1 | N | IN | BANK 3 | 62.368 |
|
|
|
|
|
|
|
A5 | VG96_IO3 | T2 | P | IN | BANK 3 | 60.667 |
B5 | VG96_IO4 | T1 | N | IN | BANK 3 | 60.664 |
|
|
|
|
|
|
|
C5 | VG96_IO5 | P4 | P | IN | BANK 3 | 57.362 |
C4 | VG96_IO2 | P3 | N | IN | BANK 3 | 57.362 |
|
|
|
|
|
|
|
A6 | VG96_IO6 | P2 | P | IN | BANK 3 | 59.397 |
B6 | VG96_IO7 | P1 | N | IN | BANK 3 | 59.394 |
|
|
|
|
|
|
|
A7 | VG96_IO9 | N2 | P | IN | BANK 3 | 59.131 |
B7 | VG96_IO10 | N1 | N | IN | BANK 3 | 59.129 |
|
|
|
|
|
|
|
C7 | VG96_IO11 | N4 | P | IN | BANK 3 | 59.244 |
C6 | VG96_IO8 | N3 | N | IN | BANK 3 | 59.232 |
|
|
|
|
|
|
|
A8 | VG96_IO12 | L2 | P | IN | BANK 3 | 58.301 |
B8 | VG96_IO13 | L1 | N | IN | BANK 3 | 58.299 |
|
|
|
|
|
|
|
A9 | VG96_IO15 | K2 | P | IN | BANK 3 | 58.238 |
B9 | VG96_IO16 | K1 | N | IN | BANK 3 | 58.236 |
|
|
|
|
|
|
|
C9 | VG96_IO17 | M3 | P | IN | BANK 3 | 59.802 |
C8 | VG96_IO14 | M1 | N | IN | BANK 3 | 59.761 |
|
|
|
|
|
|
|
A10 | VG96_IO18 | H2 | P | IN | BANK 3 | 55.682 |
B10 | VG96_IO19 | H1 | N | IN | BANK 3 | 55.680 |
|
|
|
|
|
|
|
USBS6 / |
| http://www.cesys.com/ |
User Doc V0.3 | preliminary |