Company X Accessories C1030-5510 manual Using SPI-Flash for configuration

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Additional information

Using SPI-Flash for configuration

How to store configuration data in SPI-Flash

To allow configuration of the FPGA via onboard SPI-Flash on power-up first an appropriate configuration file has to be stored in the SPI-Flash. There are several ways to accomplish this.

Loading SPI-Flash via USB

The easiest way to get data into SPI-Flash surely is to use CESYS software UDK-Lab. With the help of this easy to use tiny tool binary FPGA configuration bitstreams (*.bin) can be downloaded to onboard SPI-Flash via USB.

SPI-Flash Indirect Programming Using FPGA JTAG Chain

Since XILINXTM ISE-WebPACK version 10.1 it is possible to configure SPI-Flashes attached to the FPGA via JTAG interface. Before starting to download a design to SPI- Flash with iMPACT programming software it is necessary to prepare the required *.mcs SPI PROM file. With xapp951 XILINXTM provides an application note how to accomplish that using iMPACT or PROMGen software tools. Select 16M SPI PROM Density when asked. Thereafter connect JTAG adapter and power-up USBS6, either by connecting USB cable or via external 5V power supply. With XILINXTM parallel cable IV the led lights green if FPGA is powered on. Now start XILINXTM iMPACT, select Boundary Scan mode and follow the manual provided by XILINXTM in xapp951. Select M25P16 SPI-Flash PROM Type when asked.

SPI-Flash
M25P16	Signal Name	FPGA IO	FPGA Direction	Comment
D	MOSI	T13	Output	Master SPI Serial Data Output.
Q	MISO	R13	Input	Master SPI Serial Data Input.
S	CSO_B	V3	Output	Master SPI Chip Select Output.
C	CCLK	R15	Output	Configuration Clock.
W	WP#	--		Externally pulled HIGH via 4,7kOhm resistor.
HOLD	HOLD#	--		Externally pulled HIGH via 4,7kOhm resistor.

SPI-Flash Direct Programming using iMPACT

Out of the box Direct SPI Programming via XILINXTM download cable and iMPACT

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-60-	preliminary

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Contents USBS6 June 29Copyright information Feature list Summary of USBS6Included in delivery Block Diagram XC6SLX16-2CSG324C Fpga featuresSpartan-6TMFPGA USBS6 Top View Powering USBS6 Bus- powered USB is used as power supply input 3V@ ??? mAModes of operation ModeConfiguration Jtag connectorName Signal Name USB2.0 controllerUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A External memory Lpddr Sdram MT46H64M16LFCK-5MCB1DQ0 Peripherals SPI Flash MX25L12845EMI-10GHEX rotary DIP switch LEDsFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 External expansion connectors USB to serial Uart interfaceDirection Comment J3 VG 96-pin external expansion connector IDC 2x25-Pin external expansion connector J4 J4 IDC 2x25-Pin external expansion connectorADDIO16 Cypress FX-2 LP and USB basics Clocking Fpga designsFX-2/FPGA slave Fifo connection Introduction to example Fpga designsISE Generate Programming File Properties Gen. Opt Disclaimer of warranty Fpga source code copyright informationFpga source code license Design usbs6soc Files and modulesSrc/wishbonepkg.vhd Src/usbs6soctop.vhd Src/wbintercon.vhdSrc/wbmafx2.vhd Src/wbslbram.vhdSrc/wbslmcb.vhd Src/wbsluart.vhdSrc/xiluartmacro Src/xilmcbmigSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by the master Wishbone signals driven by slavesDesign usbs6bram ExampleSrc/usbs6bramtop.vhd Src/simtb/wbslbramtb.vhdUsbs6bram.xise Usbs6bram.ucfWbslbramtb.cmd Introduction Changes to previous versionsDriver installation WindowsRequirements Build UDKLets assume to use c\\udkapi Linux DriversPCI Makefile creation and build Preliminary Use APIs in own projects Add project to UDK buildAPI Error handling API Functions in detail++ and .NET API GetLastErrorCode Error code Kind of errorGetLastErrorText Methods/FunctionsDevice enumeration InitDeInit Enumerate DeviceType DescriptionGetDeviceCount Static unsigned int ceDeviceGetDeviceCountGetDevice Static ceDevice *ceDeviceGetDeviceunsigned int uiIdxInformation gathering GetUDKVersionStringGetDeviceUID GetDeviceNameGetBusType Constant BusGetMaxTransferSize Using devices OpenClose Void ceDeviceOpenReadRegister WriteRegisterReadBlock WriteBlockEnableInterrupt ResetFPGAWaitForInterrupt SetTimeOut ProgramFPGAFromBINProgramFPGAFromMemory ProgramFPGAFromMemoryZEnableBurst Void ceDeviceEnableBurstbool bEnableUDKLab IntroductionMain screen UDKLab Main ScreenUsing UDKLab Device selection flowFpga configuration Prepare to work with deviceFpga design flashing ProjectsSequence contents Add new initializing task Content panel Sequence startRegister entry Register panelData area entry Data area panelUsing SPI-Flash for configuration How to store configuration data in SPI-FlashM25P16 Fpga Connection Jtag Signal Name IO pairing and etch length report J3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUTNet name Direction52.506 Etch Length mm B18 J4 IDC-50 pin connector Differential pairs 17 IN/OUT Direction Fpga Bank Etch Length mm A28Addio 42.990 Mechanical dimensions USBS6 mechanical dimensions in mmTable of contents Table of Contents USB PCI ++ API