(BFM), too. These can be used for behavioral simulation purposes.
src/usbs6_soc_top.vhd:
This is the top level entity of the design. The WISHBONE components are instantiated here.
src/wb_intercon.vhd:
All WISHBONE devices are connected to this shared bus interconnection logic. Some MSBs of the address are used to select the appropriate slave.
src/wb_ma_fx2.vhd:
This is the entity of the WISHBONE master, which converts the CESYS USB protocol into one or more 32 Bit single read/write WISHBONE cycles. The low level
src/wb_sl_bram.vhd:
A internal BlockRAM is instantiated here and simply connected to the WISHBONE architecture. It can be used for testing address oriented data transactions over USB.
src/wb_sl_gpio.vhd:
This entity provides up to 256 general purpose I/Os to set and monitor
I/O signals of VG96 connector VG96_IO[80:0] are at port0 – port2, bits[80:0], I/O signals of
Port7 is used for monitoring MCB status signals bit[224] => READ ERROR, bit[225] => READ OVERFLOW, bit[226] => WRITE ERROR, bit[227] => WRITE UNDERRUN and bit[228] => CALIBRATION DONE.
src/wb_sl_flash.vhd:
The module encapsulates the low level FLASH controller flash_ctrl.vhd. The integrated command register supports the BULK ERASE command, which erases the whole memory by programming all bits to '1'. In write cycles the bit values can only be changed from '1' to '0'. That means, that it is not allowed to have a write access to the same address twice without erasing the whole flash before. The read access is as simple as reading from any other WISHBONE device. Please see the
USBS6 / |
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User Doc V0.3 | preliminary |