Company X Accessories C1030-5510 manual Src/usbs6soctop.vhd, Src/wbintercon.vhd, Src/wbmafx2.vhd

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(BFM), too. These can be used for behavioral simulation purposes.

src/usbs6_soc_top.vhd:

This is the top level entity of the design. The WISHBONE components are instantiated here.

src/wb_intercon.vhd:

All WISHBONE devices are connected to this shared bus interconnection logic. Some MSBs of the address are used to select the appropriate slave.

src/wb_ma_fx2.vhd:

This is the entity of the WISHBONE master, which converts the CESYS USB protocol into one or more 32 Bit single read/write WISHBONE cycles. The low level FX-2 slave FIFO controller (fx2_slfifo_ctrl.vhd) is used and 16/32 bit data width conversion is done by using special FIFOs (sfifo_hd_a1Kx18b0K5x36.vhd).

src/wb_sl_bram.vhd:

A internal BlockRAM is instantiated here and simply connected to the WISHBONE architecture. It can be used for testing address oriented data transactions over USB.

src/wb_sl_gpio.vhd:

This entity provides up to 256 general purpose I/Os to set and monitor non-timing-critical internal and external FPGA signals. The I/Os can be accessed as eight ports with 32 bits each. Every single I/O can be configured as an in- or output.

I/O signals of VG96 connector VG96_IO[80:0] are at port0 – port2, bits[80:0], I/O signals of add-on connector ADD_IO[33:0] are at port3 – port4, bits[129:96], user LEDs are at port5, bits[163:160] and hex encoder is at port6, bits[195:192].

Port7 is used for monitoring MCB status signals bit[224] => READ ERROR, bit[225] => READ OVERFLOW, bit[226] => WRITE ERROR, bit[227] => WRITE UNDERRUN and bit[228] => CALIBRATION DONE.

src/wb_sl_flash.vhd:

The module encapsulates the low level FLASH controller flash_ctrl.vhd. The integrated command register supports the BULK ERASE command, which erases the whole memory by programming all bits to '1'. In write cycles the bit values can only be changed from '1' to '0'. That means, that it is not allowed to have a write access to the same address twice without erasing the whole flash before. The read access is as simple as reading from any other WISHBONE device. Please see the SPI-FLASH data sheet for details on programming and erasing. There are two instances of this module. One is used for

USBS6 / C1030-5510

 

http://www.cesys.com/

User Doc V0.3

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preliminary

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Contents USBS6 June 29Copyright information Summary of USBS6 Feature listIncluded in delivery XC6SLX16-2CSG324C Fpga features Block DiagramSpartan-6TMFPGA USBS6 Top View Modes of operation Powering USBS6Bus- powered USB is used as power supply input 3V@ ??? mA ModeJtag connector ConfigurationName USB2.0 controller Signal NameUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A External memory Lpddr Sdram MT46H64M16LFCK-5MCB1DQ0 Peripherals SPI Flash MX25L12845EMI-10GLEDs HEX rotary DIP switchFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 USB to serial Uart interface External expansion connectorsDirection Comment J3 VG 96-pin external expansion connector IDC 2x25-Pin external expansion connector J4 J4 IDC 2x25-Pin external expansion connectorADDIO16 Cypress FX-2 LP and USB basics Clocking Fpga designsFX-2/FPGA slave Fifo connection Introduction to example Fpga designsISE Generate Programming File Properties Gen. Opt Fpga source code copyright information Disclaimer of warrantyFpga source code license Files and modules Design usbs6socSrc/wishbonepkg.vhd Src/wbmafx2.vhd Src/usbs6soctop.vhdSrc/wbintercon.vhd Src/wbslbram.vhdSrc/xiluartmacro Src/wbslmcb.vhdSrc/wbsluart.vhd Src/xilmcbmigSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by the master Wishbone signals driven by slavesDesign usbs6bram ExampleUsbs6bram.xise Src/usbs6bramtop.vhdSrc/simtb/wbslbramtb.vhd Usbs6bram.ucfWbslbramtb.cmd Introduction Changes to previous versionsRequirements Driver installationWindows Build UDKLets assume to use c\\udkapi Linux DriversPCI Makefile creation and build Preliminary Use APIs in own projects Add project to UDK buildAPI Functions in detail API Error handling++ and .NET API GetLastErrorText GetLastErrorCodeError code Kind of error Methods/FunctionsInit Device enumerationDeInit GetDeviceCount EnumerateDeviceType Description Static unsigned int ceDeviceGetDeviceCountGetDevice Static ceDevice *ceDeviceGetDeviceunsigned int uiIdxGetDeviceUID Information gatheringGetUDKVersionString GetDeviceNameConstant Bus GetBusTypeGetMaxTransferSize Close Using devicesOpen Void ceDeviceOpenReadBlock ReadRegisterWriteRegister WriteBlockResetFPGA EnableInterruptWaitForInterrupt ProgramFPGAFromMemory SetTimeOutProgramFPGAFromBIN ProgramFPGAFromMemoryZEnableBurst Void ceDeviceEnableBurstbool bEnableUDKLab IntroductionMain screen UDKLab Main ScreenUsing UDKLab Device selection flowFpga configuration Prepare to work with deviceFpga design flashing ProjectsSequence contents Add new initializing task Content panel Sequence startRegister entry Register panelData area entry Data area panelUsing SPI-Flash for configuration How to store configuration data in SPI-FlashM25P16 Fpga Connection Jtag Signal Name Net name IO pairing and etch length reportJ3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT Direction52.506 Etch Length mm B18 J4 IDC-50 pin connector Differential pairs 17 IN/OUT Direction Fpga Bank Etch Length mm A28Addio 42.990 Mechanical dimensions USBS6 mechanical dimensions in mmTable of contents Table of Contents USB PCI ++ API