Company X Accessories C1030-5510 manual Addio

Page 66

PIN

Net name

FPGA IO

P / N

Direction

FPGA BANK

Etch Length (mm)

13

ADD_IO

B4

P

IN / OUT

BANK 0

19.754

14

ADD_IO

A4

N

IN / OUT

BANK 0

19.743

 

 

 

 

 

 

 

15

ADD_IO

B6

P

IN / OUT

BANK 0

20.143

16

ADD_IO

A6

N

IN / OUT

BANK 0

20.131

 

 

 

 

 

 

 

19

ADD_IO

B8

P

IN / OUT

BANK 0

20.421

20

ADD_IO

A8

N

IN / OUT

BANK 0

20.394

 

 

 

 

 

 

 

21

ADD_IO

B9

P

IN / OUT

BANK 0

21.514

22

ADD_IO

A9

N

IN / OUT

BANK 0

21.497

 

 

 

 

 

 

 

25

ADD_IO

B11

P

IN / OUT

BANK 0

24.381

26

ADD_IO

A11

N

IN / OUT

BANK 0

24.354

 

 

 

 

 

 

 

27

ADD_IO

B12

P

IN / OUT

BANK 0

25.102

28

ADD_IO

A12

N

IN / OUT

BANK 0

25.137

 

 

 

 

 

 

 

29

ADD_IO

B14

P

IN / OUT

BANK 0

25.150

30

ADD_IO

A14

N

IN / OUT

BANK 0

25.137

 

 

 

 

 

 

 

31

ADD_IO

B16

P

IN / OUT

BANK 0

26.005

32

ADD_IO

A16

N

IN / OUT

BANK 0

25.980

 

 

 

 

 

 

 

35

ADD_IO

C10

P

IN / OUT

BANK 0

40.687

36

ADD_IO

A10

N

IN / OUT

BANK 0

40.669

 

 

 

 

 

 

 

37

ADD_IO

D12

P

IN / OUT

BANK 0

40.905

38

ADD_IO

C12

N

IN / OUT

BANK 0

40.865

 

 

 

 

 

 

 

41

ADD_IO

C13

P

IN / OUT

BANK 0

43.579

42

ADD_IO

A13

N

IN / OUT

BANK 0

43.527

 

 

 

 

 

 

 

43

ADD_IO

D14

P

IN / OUT

BANK 0

43.029

USBS6 / C1030-5510

 

http://www.cesys.com/

User Doc V0.3

-66-

preliminary

Image 66
Contents USBS6 June 29Copyright information Feature list Summary of USBS6Included in delivery Block Diagram XC6SLX16-2CSG324C Fpga featuresSpartan-6TMFPGA USBS6 Top View Modes of operation Powering USBS6Bus- powered USB is used as power supply input 3V@ ??? mA ModeConfiguration Jtag connectorName Signal Name USB2.0 controllerUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A External memory Lpddr Sdram MT46H64M16LFCK-5MCB1DQ0 Peripherals SPI Flash MX25L12845EMI-10GHEX rotary DIP switch LEDsFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 External expansion connectors USB to serial Uart interfaceDirection Comment J3 VG 96-pin external expansion connector IDC 2x25-Pin external expansion connector J4 J4 IDC 2x25-Pin external expansion connectorADDIO16 Cypress FX-2 LP and USB basics Clocking Fpga designsFX-2/FPGA slave Fifo connection Introduction to example Fpga designsISE Generate Programming File Properties Gen. Opt Disclaimer of warranty Fpga source code copyright informationFpga source code license Design usbs6soc Files and modulesSrc/wishbonepkg.vhd Src/wbmafx2.vhd Src/usbs6soctop.vhdSrc/wbintercon.vhd Src/wbslbram.vhdSrc/xiluartmacro Src/wbslmcb.vhdSrc/wbsluart.vhd Src/xilmcbmigSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by the master Wishbone signals driven by slavesDesign usbs6bram ExampleUsbs6bram.xise Src/usbs6bramtop.vhdSrc/simtb/wbslbramtb.vhd Usbs6bram.ucfWbslbramtb.cmd Introduction Changes to previous versionsRequirements Driver installationWindows Build UDKLets assume to use c\\udkapi Linux DriversPCI Makefile creation and build Preliminary Use APIs in own projects Add project to UDK buildAPI Error handling API Functions in detail++ and .NET API GetLastErrorText GetLastErrorCodeError code Kind of error Methods/FunctionsDevice enumeration InitDeInit GetDeviceCount EnumerateDeviceType Description Static unsigned int ceDeviceGetDeviceCountGetDevice Static ceDevice *ceDeviceGetDeviceunsigned int uiIdxGetDeviceUID Information gatheringGetUDKVersionString GetDeviceNameGetBusType Constant BusGetMaxTransferSize Close Using devicesOpen Void ceDeviceOpenReadBlock ReadRegisterWriteRegister WriteBlockEnableInterrupt ResetFPGAWaitForInterrupt ProgramFPGAFromMemory SetTimeOutProgramFPGAFromBIN ProgramFPGAFromMemoryZEnableBurst Void ceDeviceEnableBurstbool bEnableUDKLab IntroductionMain screen UDKLab Main ScreenUsing UDKLab Device selection flowFpga configuration Prepare to work with deviceFpga design flashing ProjectsSequence contents Add new initializing task Content panel Sequence startRegister entry Register panelData area entry Data area panelUsing SPI-Flash for configuration How to store configuration data in SPI-FlashM25P16 Fpga Connection Jtag Signal Name Net name IO pairing and etch length reportJ3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT Direction52.506 Etch Length mm B18 J4 IDC-50 pin connector Differential pairs 17 IN/OUT Direction Fpga Bank Etch Length mm A28Addio 42.990 Mechanical dimensions USBS6 mechanical dimensions in mmTable of contents Table of Contents USB PCI ++ API