Company X Accessories C1030-5510 manual Using UDKLab, Device selection flow

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Using UDKLab

After starting UDKLab, most of the UI components are disabled. They will be enabled at the point they make sense. As no device is selected, only device independent functions are available:

•The FPGA design array creator

•The option to define USB Power-On behavior

•Info menu contents

All other actions require a device, which can be chosen via the device selector which pops up as separate window:

Figure 12: Device selection flow

If the device list is not up to date, clicking Re-Enum will search again. A device can be selected by either double clicking on it or choosing OK.

Important: Opening the device selector again will internally re-initialize the underlying API, so active communication is stopped and the right panel is disabled again (more on the state of this panel below).

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-52-	preliminary

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Contents USBS6 June 29Copyright information Summary of USBS6 Feature listIncluded in delivery XC6SLX16-2CSG324C Fpga features Block DiagramSpartan-6TMFPGA USBS6 Top View Powering USBS6 Bus- powered USB is used as power supply input 3V@ ??? mAModes of operation ModeJtag connector ConfigurationName USB2.0 controller Signal NameUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A External memory Lpddr Sdram MT46H64M16LFCK-5MCB1DQ0 Peripherals SPI Flash MX25L12845EMI-10GLEDs HEX rotary DIP switchFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 USB to serial Uart interface External expansion connectorsDirection Comment J3 VG 96-pin external expansion connector IDC 2x25-Pin external expansion connector J4 J4 IDC 2x25-Pin external expansion connectorADDIO16 Cypress FX-2 LP and USB basics Clocking Fpga designsFX-2/FPGA slave Fifo connection Introduction to example Fpga designsISE Generate Programming File Properties Gen. Opt Fpga source code copyright information Disclaimer of warrantyFpga source code license Files and modules Design usbs6socSrc/wishbonepkg.vhd Src/usbs6soctop.vhd Src/wbintercon.vhdSrc/wbmafx2.vhd Src/wbslbram.vhdSrc/wbslmcb.vhd Src/wbsluart.vhdSrc/xiluartmacro Src/xilmcbmigSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by the master Wishbone signals driven by slavesDesign usbs6bram ExampleSrc/usbs6bramtop.vhd Src/simtb/wbslbramtb.vhdUsbs6bram.xise Usbs6bram.ucfWbslbramtb.cmd Introduction Changes to previous versionsDriver installation WindowsRequirements Build UDKLets assume to use c\\udkapi Linux DriversPCI Makefile creation and build Preliminary Use APIs in own projects Add project to UDK buildAPI Functions in detail API Error handling++ and .NET API GetLastErrorCode Error code Kind of errorGetLastErrorText Methods/FunctionsInit Device enumerationDeInit Enumerate DeviceType DescriptionGetDeviceCount Static unsigned int ceDeviceGetDeviceCountGetDevice Static ceDevice *ceDeviceGetDeviceunsigned int uiIdxInformation gathering GetUDKVersionStringGetDeviceUID GetDeviceNameConstant Bus GetBusTypeGetMaxTransferSize Using devices OpenClose Void ceDeviceOpenReadRegister WriteRegisterReadBlock WriteBlockResetFPGA EnableInterruptWaitForInterrupt SetTimeOut ProgramFPGAFromBINProgramFPGAFromMemory ProgramFPGAFromMemoryZEnableBurst Void ceDeviceEnableBurstbool bEnableUDKLab IntroductionMain screen UDKLab Main ScreenUsing UDKLab Device selection flowFpga configuration Prepare to work with deviceFpga design flashing ProjectsSequence contents Add new initializing task Content panel Sequence startRegister entry Register panelData area entry Data area panelUsing SPI-Flash for configuration How to store configuration data in SPI-FlashM25P16 Fpga Connection Jtag Signal Name IO pairing and etch length report J3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUTNet name Direction52.506 Etch Length mm B18 J4 IDC-50 pin connector Differential pairs 17 IN/OUT Direction Fpga Bank Etch Length mm A28Addio 42.990 Mechanical dimensions USBS6 mechanical dimensions in mmTable of contents Table of Contents USB PCI ++ API