Company X Accessories C1030-5510 manual ReadRegister, WriteRegister, ReadBlock, WriteBlock

Page 46

Finish working with the given device.

ReadRegister

API	Code
C++	unsigned int ceDevice::ReadRegister(unsiged int uiRegister)

CCE_RESULT ReadRegister(CE_DEVICE_HANDLE Handle, unsigned int uiRegister, unsigned int *puiValue)

.NET	uint ceDevice.ReadRegister(uint uiRegister)

Read 32 bit value from FPGA design address space (internally just calling ReadBlock() with size = 4).

WriteRegister

API	Code
C++	void ceDevice::WriteRegister(unsiged int uiRegister, unsigned int uiValue)

CCE_RESULT WriteRegister(CE_DEVICE_HANDLE Handle, unsigned int uiRegister, unsigned int uiValue)

.NET	void ceDevice.WriteRegister(uint uiRegister, uint uiValue)

Write 32 bit value to FPGA design address space (internally just calling WriteBlock() with size = 4).

ReadBlock

API	Code
C++	void ceDevice::ReadBlock(unsiged int uiAddress, unsigned char *pucData, unsigned int
	uiSize, bool bIncAddress)

CCE_RESULT ReadBlock(CE_DEVICE_HANDLE Handle, unsigned int uiAddress, unsigned char *pucData, unsigned int uiSize, unsigned int uiIncAddress)

.NET	void ceDevice.ReadBlock(uint uiAddess, byte[] Data, uint uiLen, bool bIncAddress)

Read a block of data to the host buffer which must be large enough to hold it. The size should never exceed the value retrieved by GetMaxTransferSize() for the specific device. bIncAddress is at the moment available for USB devices only. It flags to read all data from the same address instead of starting at it.

WriteBlock

API	Code
C++	void ceDevice::WriteBlock(unsiged int uiAddress, unsigned char *pucData, unsigned int
	uiSize, bool bIncAddress)

CCE_RESULT WriteBlock(CE_DEVICE_HANDLE Handle, unsigned int uiAddress,

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-46-	preliminary

Image 46

Contents USBS6 June 29Copyright information Summary of USBS6 Feature listIncluded in delivery XC6SLX16-2CSG324C Fpga features Block DiagramSpartan-6TMFPGA USBS6 Top View Modes of operation Powering USBS6Bus- powered USB is used as power supply input 3V@ ??? mA ModeJtag connector ConfigurationName USB2.0 controller Signal NameUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A External memory Lpddr Sdram MT46H64M16LFCK-5MCB1DQ0 Peripherals SPI Flash MX25L12845EMI-10GLEDs HEX rotary DIP switchFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 USB to serial Uart interface External expansion connectorsDirection Comment J3 VG 96-pin external expansion connector IDC 2x25-Pin external expansion connector J4 J4 IDC 2x25-Pin external expansion connectorADDIO16 Cypress FX-2 LP and USB basics Clocking Fpga designsFX-2/FPGA slave Fifo connection Introduction to example Fpga designsISE Generate Programming File Properties Gen. Opt Fpga source code copyright information Disclaimer of warrantyFpga source code license Files and modules Design usbs6socSrc/wishbonepkg.vhd Src/wbmafx2.vhd Src/usbs6soctop.vhdSrc/wbintercon.vhd Src/wbslbram.vhdSrc/xiluartmacro Src/wbslmcb.vhdSrc/wbsluart.vhd Src/xilmcbmigSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by the master Wishbone signals driven by slavesDesign usbs6bram ExampleUsbs6bram.xise Src/usbs6bramtop.vhdSrc/simtb/wbslbramtb.vhd Usbs6bram.ucfWbslbramtb.cmd Introduction Changes to previous versionsRequirements Driver installationWindows Build UDKLets assume to use c\\udkapi Linux DriversPCI Makefile creation and build Preliminary Use APIs in own projects Add project to UDK buildAPI Functions in detail API Error handling++ and .NET API GetLastErrorText GetLastErrorCodeError code Kind of error Methods/FunctionsInit Device enumerationDeInit GetDeviceCount EnumerateDeviceType Description Static unsigned int ceDeviceGetDeviceCountGetDevice Static ceDevice *ceDeviceGetDeviceunsigned int uiIdxGetDeviceUID Information gatheringGetUDKVersionString GetDeviceNameConstant Bus GetBusTypeGetMaxTransferSize Close Using devicesOpen Void ceDeviceOpenReadBlock ReadRegisterWriteRegister WriteBlockResetFPGA EnableInterruptWaitForInterrupt ProgramFPGAFromMemory SetTimeOutProgramFPGAFromBIN ProgramFPGAFromMemoryZEnableBurst Void ceDeviceEnableBurstbool bEnableUDKLab IntroductionMain screen UDKLab Main ScreenUsing UDKLab Device selection flowFpga configuration Prepare to work with deviceFpga design flashing ProjectsSequence contents Add new initializing task Content panel Sequence startRegister entry Register panelData area entry Data area panelUsing SPI-Flash for configuration How to store configuration data in SPI-FlashM25P16 Fpga Connection Jtag Signal Name Net name IO pairing and etch length reportJ3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT Direction52.506 Etch Length mm B18 J4 IDC-50 pin connector Differential pairs 17 IN/OUT Direction Fpga Bank Etch Length mm A28Addio 42.990 Mechanical dimensions USBS6 mechanical dimensions in mmTable of contents Table of Contents USB PCI ++ API