Company X Accessories C1030-5510 manual J4 IDC-50 pin connector Differential pairs 17 IN/OUT

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PIN

Net name

FPGA IO

P / N

Direction FPGA BANK Etch Length (mm)

A28	VG96_IO69	G11	P	IN / OUT	BANK 0	73.791
B28	VG96_IO70	F10	N	IN / OUT	BANK 0	73.594

C28	VG96_IO71	G8	P	IN / OUT	BANK 0	69.296
C27	VG96_IO68	F8	N	IN / OUT	BANK 0	69.246

A29	VG96_IO72	D11	P	IN / OUT	BANK 0	72.405
B29	VG96_IO73	C11	N	IN / OUT	BANK 0	72.379

A30	VG96_IO75	F12	P	IN / OUT	BANK 0	74.452
B30	VG96_IO76	E12	N	IN / OUT	BANK 0	74.253

C30	VG96_IO77	F11	P	IN / OUT	BANK 0	68.952
C29	VG96_IO74	E11	N	IN / OUT	BANK 0	68.755

A31	VG96_IO78	F13	P	IN / OUT	BANK 0	75.068
B31	VG96_IO79	E13	N	IN / OUT	BANK 0	74.871

J4 IDC-50 pin connector - Differential pairs (17 IN/OUT)

PIN	Net name	FPGA IO	P / N	Direction	FPGA BANK	Etch Length (mm)
3	ADD_IO	C5	P	IN / OUT	BANK 0	30.618
4	ADD_IO	A5	N	IN / OUT	BANK 0	30.458

5	ADD_IO	C7	P	IN / OUT	BANK 0	28.054
6	ADD_IO	A7	N	IN / OUT	BANK 0	28.005

9	ADD_IO	B2	P	IN / OUT	BANK 0	18.486
10	ADD_IO	A2	N	IN / OUT	BANK 0	18.461

11	ADD_IO	B3	P	IN / OUT	BANK 0	19.033
12	ADD_IO	A3	N	IN / OUT	BANK 0	19.021

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-65-	preliminary

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Contents June 29 USBS6Copyright information Included in delivery Feature listSummary of USBS6 Spartan-6TMFPGA Block DiagramXC6SLX16-2CSG324C Fpga features USBS6 Top View Bus- powered USB is used as power supply input 3V@ ??? mA Powering USBS6Modes of operation ModeName ConfigurationJtag connector USB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A Signal NameUSB2.0 controller Lpddr Sdram MT46H64M16LFCK-5 External memoryMCB1DQ0 SPI Flash MX25L12845EMI-10G PeripheralsFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 HEX rotary DIP switchLEDs Direction Comment External expansion connectorsUSB to serial Uart interface J3 VG 96-pin external expansion connector J4 IDC 2x25-Pin external expansion connector IDC 2x25-Pin external expansion connector J4ADDIO16 Clocking Fpga designs Cypress FX-2 LP and USB basicsIntroduction to example Fpga designs FX-2/FPGA slave Fifo connectionISE Generate Programming File Properties Gen. Opt Fpga source code license Disclaimer of warrantyFpga source code copyright information Src/wishbonepkg.vhd Design usbs6socFiles and modules Src/wbintercon.vhd Src/usbs6soctop.vhdSrc/wbmafx2.vhd Src/wbslbram.vhdSrc/wbsluart.vhd Src/wbslmcb.vhdSrc/xiluartmacro Src/xilmcbmigSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by slaves Wishbone signals driven by the masterExample Design usbs6bramSrc/simtb/wbslbramtb.vhd Src/usbs6bramtop.vhdUsbs6bram.xise Usbs6bram.ucfWbslbramtb.cmd Changes to previous versions IntroductionWindows Driver installationRequirements Build UDKLets assume to use c\\udkapi Drivers LinuxPCI Makefile creation and build Preliminary Add project to UDK build Use APIs in own projects++ and .NET API API Error handlingAPI Functions in detail Error code Kind of error GetLastErrorCodeGetLastErrorText Methods/FunctionsDeInit Device enumerationInit DeviceType Description EnumerateGetDeviceCount Static unsigned int ceDeviceGetDeviceCountStatic ceDevice *ceDeviceGetDeviceunsigned int uiIdx GetDeviceGetUDKVersionString Information gatheringGetDeviceUID GetDeviceNameGetMaxTransferSize GetBusTypeConstant Bus Open Using devicesClose Void ceDeviceOpenWriteRegister ReadRegisterReadBlock WriteBlockWaitForInterrupt EnableInterruptResetFPGA ProgramFPGAFromBIN SetTimeOutProgramFPGAFromMemory ProgramFPGAFromMemoryZVoid ceDeviceEnableBurstbool bEnable EnableBurstIntroduction UDKLabUDKLab Main Screen Main screenDevice selection flow Using UDKLabPrepare to work with device Fpga configurationProjects Fpga design flashingSequence contents Add new initializing task Sequence start Content panelRegister panel Register entryData area panel Data area entryHow to store configuration data in SPI-Flash Using SPI-Flash for configurationM25P16 Fpga Connection Jtag Signal Name J3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT IO pairing and etch length reportNet name Direction52.506 Etch Length mm B18 Direction Fpga Bank Etch Length mm A28 J4 IDC-50 pin connector Differential pairs 17 IN/OUTAddio 42.990 USBS6 mechanical dimensions in mm Mechanical dimensionsTable of contents Table of Contents USB PCI ++ API