Company X Accessories C1030-5510 manual Peripherals, SPI Flash MX25L12845EMI-10G

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LPDDR SDRAM MT46H64M16LFCK-5

Signal Name	FPGA IO	Comment
MCB1_DQ12	T17
MCB1_DQ13	T18
MCB1_DQ14	U17
MCB1_DQ15	U18
MCB1_UDQS	N15	Data strobe for Upper Byte Data bus: Output with read data, input
		with write data. DQS is edge-aligned with read data, center-aligned in
		write data. It is used to capture data.

*As the memory device interface of Spartan-6 supports only one device, CS# signal is not supported by Spartan-6 MCB. CS# is pulled LOW via an external 0 Ohm resistor.

!It is strongly recommended to check XILINXTM user guide UG388 about Spartan-6TMFPGA Memory Controller on XILINXTM website.

!It is strongly recommended to check XILINXTM user guide UG416 about Spartan-6TMFPGA Memory Interface Solutions on XILINXTM website.

User specific data can be stored in up to 128Mb of non-volatile Flash-memory. The SPI- compliant interface guarantees ease of use and when speed matters

Macronix MX25L12845EMI-10G supports Q- SPI with data-rates up to 50 MByte/s in fast read double transfer rate mode. Some examples on how to implement a SPI- compliant interface with Spartan-6TMare available in chapter C.

Q- SPI Flash MX25L12845EMI-10G

Signal Name	FPGA IO	Comment

MX_CS_n	T6	Active- low Chip Select.
MX_SCLK	V4	Clock Input.
MX_SIO0	V6	Serial Data Input (SPI) / Serial Data IO (Dual- or Q- SPI).
MX_SIO1	T4	Serial Data Input (SPI) / Serial Data IO (Dual- or Q- SPI).
MX_SIO2	U7	Active- low Write Protect (SPI) / Serial Data IO (Dual- or Q-SPI).
MX_SIO3	V7	Not connect pin (SPI) / Serial Data IO (Dual- or Q-SPI).

Peripherals

USBS6 integrates several peripheral devices. Three system and five user- configurable LEDs, one HEX rotary DIP switch and one USB to SERIAL UART are available. Power supply status and FPGA configuration are observable through the system LEDs. The user-

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-11-	preliminary

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Contents June 29 USBS6Copyright information Included in delivery Feature listSummary of USBS6 Spartan-6TMFPGA Block DiagramXC6SLX16-2CSG324C Fpga features USBS6 Top View Mode Powering USBS6Bus- powered USB is used as power supply input 3V@ ??? mA Modes of operationName ConfigurationJtag connector USB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A Signal NameUSB2.0 controller Lpddr Sdram MT46H64M16LFCK-5 External memoryMCB1DQ0 SPI Flash MX25L12845EMI-10G PeripheralsFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 HEX rotary DIP switchLEDs Direction Comment External expansion connectorsUSB to serial Uart interface J3 VG 96-pin external expansion connector J4 IDC 2x25-Pin external expansion connector IDC 2x25-Pin external expansion connector J4ADDIO16 Clocking Fpga designs Cypress FX-2 LP and USB basicsIntroduction to example Fpga designs FX-2/FPGA slave Fifo connectionISE Generate Programming File Properties Gen. Opt Fpga source code license Disclaimer of warrantyFpga source code copyright information Src/wishbonepkg.vhd Design usbs6socFiles and modules Src/wbslbram.vhd Src/usbs6soctop.vhdSrc/wbintercon.vhd Src/wbmafx2.vhdSrc/xilmcbmig Src/wbslmcb.vhdSrc/wbsluart.vhd Src/xiluartmacroSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by slaves Wishbone signals driven by the masterExample Design usbs6bramUsbs6bram.ucf Src/usbs6bramtop.vhdSrc/simtb/wbslbramtb.vhd Usbs6bram.xiseWbslbramtb.cmd Changes to previous versions IntroductionBuild UDK Driver installationWindows RequirementsLets assume to use c\\udkapi Drivers LinuxPCI Makefile creation and build Preliminary Add project to UDK build Use APIs in own projects++ and .NET API API Error handlingAPI Functions in detail Methods/Functions GetLastErrorCodeError code Kind of error GetLastErrorTextDeInit Device enumerationInit Static unsigned int ceDeviceGetDeviceCount EnumerateDeviceType Description GetDeviceCountStatic ceDevice *ceDeviceGetDeviceunsigned int uiIdx GetDeviceGetDeviceName Information gatheringGetUDKVersionString GetDeviceUIDGetMaxTransferSize GetBusTypeConstant Bus Void ceDeviceOpen Using devicesOpen CloseWriteBlock ReadRegisterWriteRegister ReadBlockWaitForInterrupt EnableInterruptResetFPGA ProgramFPGAFromMemoryZ SetTimeOutProgramFPGAFromBIN ProgramFPGAFromMemoryVoid ceDeviceEnableBurstbool bEnable EnableBurstIntroduction UDKLabUDKLab Main Screen Main screenDevice selection flow Using UDKLabPrepare to work with device Fpga configurationProjects Fpga design flashingSequence contents Add new initializing task Sequence start Content panelRegister panel Register entryData area panel Data area entryHow to store configuration data in SPI-Flash Using SPI-Flash for configurationM25P16 Fpga Connection Jtag Signal Name Direction IO pairing and etch length reportJ3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT Net name52.506 Etch Length mm B18 Direction Fpga Bank Etch Length mm A28 J4 IDC-50 pin connector Differential pairs 17 IN/OUTAddio 42.990 USBS6 mechanical dimensions in mm Mechanical dimensionsTable of contents Table of Contents USB PCI ++ API