Company X Accessories C1030-5510 manual Summary of USBS6, Feature list, Included in delivery

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Overview

Summary of USBS6

USBS6 is a low-cost multilayer PCB with SPARTAN-6TMFPGA and USB 2.0 Interface. 34 I/O balls of the FPGA are available on standard 2.54mm headers, 81 I/O balls can be reached through a industry standard VG 96-pin connector. It offers multiple configuration options including USB and onboard SPI-Flash and can also be used standalone without the need of a USB interface.

Feature list

Form factor	120x100mm
XILINX SPARTAN-6TM	XC6SLX16-2CSG324C
USB2.0 Controller	CYPRESSTM CY7C68013A
FPGA configuration	Using USB2.0, JTAG or SPI-Flash
Memory	16Mb SPI-Flash Numonyx M25P16,
	128Mb Quad-SPI-Flash Macronix MX25L12845EMI-10G,
	1Gb low-power DDR SDRAM Micron
	Technology MT46H64M16LFCK-5
Peripherals	USB TO SERIAL UART FTDI FT232R,
	HEX rotary DIP switch,
	3 status, 5 user LEDs
Expansion connectors	2x25-Pin standard RM2.54mm header,
	VG 96-pin connector
Clock	Onboard 48MHz clock signal,
	up to two optional onboard clocks,
	external clock sources possible.

Included in delivery

The standard delivery, order no. C1030-5510, includes:

•One USBS6

•One USB cable 1,5m

•One CD-ROM containing the user's manual (English), drivers, libraries, tools and example source code.

All parts are ROHS compliant.

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-3-	preliminary

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Contents June 29 USBS6Copyright information Feature list Summary of USBS6Included in delivery Block Diagram XC6SLX16-2CSG324C Fpga featuresSpartan-6TMFPGA USBS6 Top View Mode Powering USBS6Bus- powered USB is used as power supply input 3V@ ??? mA Modes of operationConfiguration Jtag connectorName Signal Name USB2.0 controllerUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A Lpddr Sdram MT46H64M16LFCK-5 External memoryMCB1DQ0 SPI Flash MX25L12845EMI-10G PeripheralsHEX rotary DIP switch LEDsFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 External expansion connectors USB to serial Uart interfaceDirection Comment J3 VG 96-pin external expansion connector J4 IDC 2x25-Pin external expansion connector IDC 2x25-Pin external expansion connector J4ADDIO16 Clocking Fpga designs Cypress FX-2 LP and USB basicsIntroduction to example Fpga designs FX-2/FPGA slave Fifo connectionISE Generate Programming File Properties Gen. Opt Disclaimer of warranty Fpga source code copyright informationFpga source code license Design usbs6soc Files and modulesSrc/wishbonepkg.vhd Src/wbslbram.vhd Src/usbs6soctop.vhdSrc/wbintercon.vhd Src/wbmafx2.vhdSrc/xilmcbmig Src/wbslmcb.vhdSrc/wbsluart.vhd Src/xiluartmacroSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by slaves Wishbone signals driven by the masterExample Design usbs6bramUsbs6bram.ucf Src/usbs6bramtop.vhdSrc/simtb/wbslbramtb.vhd Usbs6bram.xiseWbslbramtb.cmd Changes to previous versions IntroductionBuild UDK Driver installationWindows RequirementsLets assume to use c\\udkapi Drivers LinuxPCI Makefile creation and build Preliminary Add project to UDK build Use APIs in own projectsAPI Error handling API Functions in detail++ and .NET API Methods/Functions GetLastErrorCodeError code Kind of error GetLastErrorTextDevice enumeration InitDeInit Static unsigned int ceDeviceGetDeviceCount EnumerateDeviceType Description GetDeviceCountStatic ceDevice *ceDeviceGetDeviceunsigned int uiIdx GetDeviceGetDeviceName Information gatheringGetUDKVersionString GetDeviceUIDGetBusType Constant BusGetMaxTransferSize Void ceDeviceOpen Using devicesOpen CloseWriteBlock ReadRegisterWriteRegister ReadBlockEnableInterrupt ResetFPGAWaitForInterrupt ProgramFPGAFromMemoryZ SetTimeOutProgramFPGAFromBIN ProgramFPGAFromMemoryVoid ceDeviceEnableBurstbool bEnable EnableBurstIntroduction UDKLabUDKLab Main Screen Main screenDevice selection flow Using UDKLabPrepare to work with device Fpga configurationProjects Fpga design flashingSequence contents Add new initializing task Sequence start Content panelRegister panel Register entryData area panel Data area entryHow to store configuration data in SPI-Flash Using SPI-Flash for configurationM25P16 Fpga Connection Jtag Signal Name Direction IO pairing and etch length reportJ3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT Net name52.506 Etch Length mm B18 Direction Fpga Bank Etch Length mm A28 J4 IDC-50 pin connector Differential pairs 17 IN/OUTAddio 42.990 USBS6 mechanical dimensions in mm Mechanical dimensionsTable of contents Table of Contents USB PCI ++ API