FPGA the reader is encouraged to take a look at the user guide UG380 on XILINXTM web page.
USB2.0 controller
CYPRESSTM FX2LPTM is a highly integrated, low power USB2.0 microcontroller, that integrates USB2.0 transceiver, serial interface engine (SIE), enhanced 8051 micro- controller and a programmable peripheral interface. More information on usage of FX2LPTM in conjunction with
USB2.0 FX2LPTM Microcontroller CYPRESSTM CY7C68013A
| Signal Name | FPGA IO | Comment |
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| FX2_IFCLK | V9 | Clock input for both, FX2 and FPGA. 48MHz clock is provided by an |
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| external oscillator. |
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| FX2_SLWR | U8 | FX2 input, FIFO |
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| FX2_SLRD | T7 | FX2 input, FIFO |
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| FX2_SLOE | V11 | FX2 input, |
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| FX2_PKTEND | V8 | FX2 input, packet end control signal, causes FX2 to send data to host |
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| at once, ignoring 512 byte alignment (so called “short packet”). |
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| ! Short packets sometimes lead to unpredictable behavior at host |
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| side, wherefore short packets are not support! |
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| FX2_FIFOADR0 | R10 | FX2 input, endpoint buffer addresses, only two endpoints are used: |
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| FX2_FIFOADR1 | U3 | EP2 (OUT, ADR[1:0] = b”00”) and EP6 (IN, ADR[1:0] = b”10”). |
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| FX2_FLAGA | V16 | FX2 output, EP2 “empty” flag. |
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| FX2_FLAGB | U16 | FX2 output, EP2 “almost empty” flag. |
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| FX2_FLAGC | U11 | FX2 output, EP6 “almost full” flag. |
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| FX2_FD0 | R11 |
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| FX2_FD1 | T14 |
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| FX2_FD2 | V14 |
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| FX2_FD3 | U5 |
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| FX2_FD4 | V5 |
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| FX2_FD5 | R3 |
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| FX2_FD6 | T3 |
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| FX2_FD7 | R5 |
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| FX2_FD8 | N5 |
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| FX2_FD9 | P6 |
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| FX2_FD10 | P12 |
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USBS6 / |
| http://www.cesys.com/ | |||
User Doc V0.3 |
| preliminary |