Company X Accessories C1030-5510 manual USB2.0 controller, Signal Name

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FPGA the reader is encouraged to take a look at the user guide UG380 on XILINXTM web page.

USB2.0 controller

CYPRESSTM FX2LPTM is a highly integrated, low power USB2.0 microcontroller, that integrates USB2.0 transceiver, serial interface engine (SIE), enhanced 8051 micro- controller and a programmable peripheral interface. More information on usage of FX2LPTM in conjunction with Spartan-6 can be found in chapter C.

USB2.0 FX2LPTM Microcontroller CYPRESSTM CY7C68013A

 

Signal Name

FPGA IO

Comment

 

 

 

 

 

 

 

 

FX2_IFCLK

V9

Clock input for both, FX2 and FPGA. 48MHz clock is provided by an

 

 

 

 

external oscillator.

 

 

 

FX2_SLWR

U8

FX2 input, FIFO write-strobe.

 

 

 

FX2_SLRD

T7

FX2 input, FIFO read-strobe.

 

 

 

FX2_SLOE

V11

FX2 input, output-enable, activates FX2 data bus.

 

 

 

FX2_PKTEND

V8

FX2 input, packet end control signal, causes FX2 to send data to host

 

 

 

 

at once, ignoring 512 byte alignment (so called “short packet”).

 

 

 

 

 

! Short packets sometimes lead to unpredictable behavior at host

 

 

 

 

side, wherefore short packets are not support!

 

 

 

FX2_FIFOADR0

R10

FX2 input, endpoint buffer addresses, only two endpoints are used:

 

 

FX2_FIFOADR1

U3

EP2 (OUT, ADR[1:0] = b”00”) and EP6 (IN, ADR[1:0] = b”10”).

 

 

 

FX2_FLAGA

V16

FX2 output, EP2 “empty” flag.

 

 

 

FX2_FLAGB

U16

FX2 output, EP2 “almost empty” flag.

 

 

 

FX2_FLAGC

U11

FX2 output, EP6 “almost full” flag.

 

 

 

FX2_FD0

R11

16-Bit bidirectional FIFO data bus.

 

 

 

FX2_FD1

T14

 

 

 

 

FX2_FD2

V14

 

 

 

 

FX2_FD3

U5

 

 

 

 

FX2_FD4

V5

 

 

 

 

FX2_FD5

R3

 

 

 

 

FX2_FD6

T3

 

 

 

 

FX2_FD7

R5

 

 

 

 

FX2_FD8

N5

 

 

 

 

FX2_FD9

P6

 

 

 

 

FX2_FD10

P12

 

 

 

 

 

 

 

 

USBS6 / C1030-5510

 

http://www.cesys.com/

User Doc V0.3

 

-8-

preliminary

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Contents USBS6 June 29Copyright information Included in delivery Feature listSummary of USBS6 Spartan-6TMFPGA Block DiagramXC6SLX16-2CSG324C Fpga features USBS6 Top View Powering USBS6 Bus- powered USB is used as power supply input 3V@ ??? mAModes of operation ModeName ConfigurationJtag connector USB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A Signal NameUSB2.0 controller External memory Lpddr Sdram MT46H64M16LFCK-5MCB1DQ0 Peripherals SPI Flash MX25L12845EMI-10GFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 HEX rotary DIP switchLEDs Direction Comment External expansion connectorsUSB to serial Uart interface J3 VG 96-pin external expansion connector IDC 2x25-Pin external expansion connector J4 J4 IDC 2x25-Pin external expansion connectorADDIO16 Cypress FX-2 LP and USB basics Clocking Fpga designsFX-2/FPGA slave Fifo connection Introduction to example Fpga designsISE Generate Programming File Properties Gen. Opt Fpga source code license Disclaimer of warrantyFpga source code copyright information Src/wishbonepkg.vhd Design usbs6socFiles and modules Src/usbs6soctop.vhd Src/wbintercon.vhdSrc/wbmafx2.vhd Src/wbslbram.vhdSrc/wbslmcb.vhd Src/wbsluart.vhdSrc/xiluartmacro Src/xilmcbmigSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by the master Wishbone signals driven by slavesDesign usbs6bram ExampleSrc/usbs6bramtop.vhd Src/simtb/wbslbramtb.vhdUsbs6bram.xise Usbs6bram.ucfWbslbramtb.cmd Introduction Changes to previous versionsDriver installation WindowsRequirements Build UDKLets assume to use c\\udkapi Linux DriversPCI Makefile creation and build Preliminary Use APIs in own projects Add project to UDK build++ and .NET API API Error handlingAPI Functions in detail GetLastErrorCode Error code Kind of errorGetLastErrorText Methods/FunctionsDeInit Device enumerationInit Enumerate DeviceType DescriptionGetDeviceCount Static unsigned int ceDeviceGetDeviceCountGetDevice Static ceDevice *ceDeviceGetDeviceunsigned int uiIdxInformation gathering GetUDKVersionStringGetDeviceUID GetDeviceNameGetMaxTransferSize GetBusTypeConstant Bus Using devices OpenClose Void ceDeviceOpenReadRegister WriteRegisterReadBlock WriteBlockWaitForInterrupt EnableInterruptResetFPGA SetTimeOut ProgramFPGAFromBINProgramFPGAFromMemory ProgramFPGAFromMemoryZEnableBurst Void ceDeviceEnableBurstbool bEnableUDKLab IntroductionMain screen UDKLab Main ScreenUsing UDKLab Device selection flowFpga configuration Prepare to work with deviceFpga design flashing ProjectsSequence contents Add new initializing task Content panel Sequence startRegister entry Register panelData area entry Data area panelUsing SPI-Flash for configuration How to store configuration data in SPI-FlashM25P16 Fpga Connection Jtag Signal Name IO pairing and etch length report J3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUTNet name Direction52.506 Etch Length mm B18 J4 IDC-50 pin connector Differential pairs 17 IN/OUT Direction Fpga Bank Etch Length mm A28Addio 42.990 Mechanical dimensions USBS6 mechanical dimensions in mmTable of contents Table of Contents USB PCI ++ API