Company X Accessories C1030-5510 manual J3 VG 96-pin external expansion connector

Page 14

Figure 5: VG 96-pin external expansion connector J3

	J3 VG 96-pin external expansion connector
	PIN	FPGA		Comment	PIN	FPGA	Comment	PIN	FPGA	Comment
		IO				IO			IO
	A32	--		GND	B32	--	GND	C32	--	GND
	A31	F13		VG96_IO78	B31	E13	VG96_IO79	C31	C4	VG96_IO80
	A30	F12		VG96_IO75	B30	E12	VG96_IO76	C30	F11	VG96_IO77
	A29	D11		VG96_IO72*	B29	C11	VG96_IO73*	C29	E11	VG96_IO74
	A28	G11		VG96_IO69	B28	F10	VG96_IO70	C28	G8	VG96_IO71
	A27	G9		VG96_IO66	B27	F9	VG96_IO67	C27	F8	VG96_IO68
	A26	D9		VG96_IO63*	B26	C9	VG96_IO64*	C26	D8	VG96_IO65
	A25	E7		VG96_IO60	B25	E8	VG96_IO61	C25	C8	VG96_IO62
	A24	D6		VG96_IO57	B24	C6	VG96_IO58	C24	F7	VG96_IO59
	A23	F6		VG96_IO54	B23	F5	VG96_IO55	C23	E6	VG96_IO56
	A22	--		GND	B22	--	GND	C22	--	GND
	A21	E4		VG96_IO51	B21	D3	VG96_IO52	C21	F4	VG96_IO53
	A20	H7		VG96_IO48	B20	G6	VG96_IO49	C20	F3	VG96_IO50
	A19	H4		VG96_IO45*	B19	H3	VG96_IO46*	C19	J7	VG96_IO47
	A18	H6		VG96_IO42	B18	H5	VG96_IO43	C18	J6	VG96_IO44
	A17	K4		VG96_IO39*	B17	K3	VG96_IO40*	C17	L6	VG96_IO41
	A16	L7		VG96_IO36	B16	K6	VG96_IO37	C16	M5	VG96_IO38
	A15	L5		VG96_IO33*	B15	K5	VG96_IO34*	C15	E3	VG96_IO35
	A14	L4		VG96_IO30	B14	L3	VG96_IO31	C14	E1	VG96_IO32
	A13	C2		VG96_IO27	B13	C1	VG96_IO28	C13	G3	VG96_IO29
	A12	D2		VG96_IO24	B12	D1	VG96_IO25	C12	G1	VG96_IO26
	A11	F2		VG96_IO21	B11	F1	VG96_IO22	C11	J3	VG96_IO23
	A10	H2		VG96_IO18*	B10	H1	VG96_IO19*	C10	J1	VG96_IO20
	A9	K2		VG96_IO15	B9	K1	VG96_IO16	C9	M3	VG96_IO17
	A8	L2		VG96_IO12	B8	L1	VG96_IO13	C8	M1	VG96_IO14

USBS6 / C1030-5510										http://www.cesys.com/
User Doc V0.3							-14-			preliminary

Image 14

Contents USBS6 June 29Copyright information Included in delivery Feature listSummary of USBS6 Spartan-6TMFPGA Block DiagramXC6SLX16-2CSG324C Fpga features USBS6 Top View Modes of operation Powering USBS6Bus- powered USB is used as power supply input 3V@ ??? mA ModeName ConfigurationJtag connector USB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A Signal NameUSB2.0 controller External memory Lpddr Sdram MT46H64M16LFCK-5MCB1DQ0 Peripherals SPI Flash MX25L12845EMI-10GFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 HEX rotary DIP switchLEDs Direction Comment External expansion connectorsUSB to serial Uart interface J3 VG 96-pin external expansion connector IDC 2x25-Pin external expansion connector J4 J4 IDC 2x25-Pin external expansion connectorADDIO16 Cypress FX-2 LP and USB basics Clocking Fpga designsFX-2/FPGA slave Fifo connection Introduction to example Fpga designsISE Generate Programming File Properties Gen. Opt Fpga source code license Disclaimer of warrantyFpga source code copyright information Src/wishbonepkg.vhd Design usbs6socFiles and modules Src/wbmafx2.vhd Src/usbs6soctop.vhdSrc/wbintercon.vhd Src/wbslbram.vhdSrc/xiluartmacro Src/wbslmcb.vhdSrc/wbsluart.vhd Src/xilmcbmigSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by the master Wishbone signals driven by slavesDesign usbs6bram ExampleUsbs6bram.xise Src/usbs6bramtop.vhdSrc/simtb/wbslbramtb.vhd Usbs6bram.ucfWbslbramtb.cmd Introduction Changes to previous versionsRequirements Driver installationWindows Build UDKLets assume to use c\\udkapi Linux DriversPCI Makefile creation and build Preliminary Use APIs in own projects Add project to UDK build++ and .NET API API Error handlingAPI Functions in detail GetLastErrorText GetLastErrorCodeError code Kind of error Methods/FunctionsDeInit Device enumerationInit GetDeviceCount EnumerateDeviceType Description Static unsigned int ceDeviceGetDeviceCountGetDevice Static ceDevice *ceDeviceGetDeviceunsigned int uiIdxGetDeviceUID Information gatheringGetUDKVersionString GetDeviceNameGetMaxTransferSize GetBusTypeConstant Bus Close Using devicesOpen Void ceDeviceOpenReadBlock ReadRegisterWriteRegister WriteBlockWaitForInterrupt EnableInterruptResetFPGA ProgramFPGAFromMemory SetTimeOutProgramFPGAFromBIN ProgramFPGAFromMemoryZEnableBurst Void ceDeviceEnableBurstbool bEnableUDKLab IntroductionMain screen UDKLab Main ScreenUsing UDKLab Device selection flowFpga configuration Prepare to work with deviceFpga design flashing ProjectsSequence contents Add new initializing task Content panel Sequence startRegister entry Register panelData area entry Data area panelUsing SPI-Flash for configuration How to store configuration data in SPI-FlashM25P16 Fpga Connection Jtag Signal Name Net name IO pairing and etch length reportJ3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT Direction52.506 Etch Length mm B18 J4 IDC-50 pin connector Differential pairs 17 IN/OUT Direction Fpga Bank Etch Length mm A28Addio 42.990 Mechanical dimensions USBS6 mechanical dimensions in mmTable of contents Table of Contents USB PCI ++ API