Company X Accessories C1030-5510 manual Register entry, Register panel

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Register entry

A register entry can be used to communicate with a 32 bit register inside the FPGA. In UDKLab, a register consists of the following values:

Address

Name

Info text

The visual representation of one register can be seen in the following image:

Figure 18: Register panel

The left buttons are responsible for adding new entries, move the entry up or down and removing the current entry, all are self explanatory. The header shows it's mapping name as well as the 32 bit address. The question mark in the lower right will show a tooltip if the mouse is above it, which is just a little help for users. Both input fields can be used to write in a new value, either hex- or decimal or contain the values if they are read from FPGA design. The checkboxes represent one bit of the current value. Clicking the Read button will read the current value from FPGA and update both text boxes as well as the checkboxes, which is automatically done every 100ms if the Auto button is active. Setting register values inside the FPGA is done in a similar way, clicking the Write button writes the current values to the device. One thing needs a bit attention here:

Clicking on the checkboxes implicitly writes the value without the need to click on the Write button !

USBS6 / C1030-5510

 

http://www.cesys.com/

User Doc V0.3

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preliminary

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Contents USBS6 June 29Copyright information Summary of USBS6 Feature listIncluded in delivery XC6SLX16-2CSG324C Fpga features Block DiagramSpartan-6TMFPGA USBS6 Top View Modes of operation Powering USBS6Bus- powered USB is used as power supply input 3V@ ??? mA ModeJtag connector ConfigurationName USB2.0 controller Signal NameUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A External memory Lpddr Sdram MT46H64M16LFCK-5MCB1DQ0 Peripherals SPI Flash MX25L12845EMI-10GLEDs HEX rotary DIP switchFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 USB to serial Uart interface External expansion connectorsDirection Comment J3 VG 96-pin external expansion connector IDC 2x25-Pin external expansion connector J4 J4 IDC 2x25-Pin external expansion connectorADDIO16 Cypress FX-2 LP and USB basics Clocking Fpga designsFX-2/FPGA slave Fifo connection Introduction to example Fpga designsISE Generate Programming File Properties Gen. Opt Fpga source code copyright information Disclaimer of warrantyFpga source code license Files and modules Design usbs6socSrc/wishbonepkg.vhd Src/wbmafx2.vhd Src/usbs6soctop.vhdSrc/wbintercon.vhd Src/wbslbram.vhdSrc/xiluartmacro Src/wbslmcb.vhdSrc/wbsluart.vhd Src/xilmcbmigSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by the master Wishbone signals driven by slavesDesign usbs6bram ExampleUsbs6bram.xise Src/usbs6bramtop.vhdSrc/simtb/wbslbramtb.vhd Usbs6bram.ucfWbslbramtb.cmd Introduction Changes to previous versionsRequirements Driver installationWindows Build UDKLets assume to use c\\udkapi Linux DriversPCI Makefile creation and build Preliminary Use APIs in own projects Add project to UDK buildAPI Functions in detail API Error handling++ and .NET API GetLastErrorText GetLastErrorCodeError code Kind of error Methods/FunctionsInit Device enumerationDeInit GetDeviceCount EnumerateDeviceType Description Static unsigned int ceDeviceGetDeviceCountGetDevice Static ceDevice *ceDeviceGetDeviceunsigned int uiIdxGetDeviceUID Information gatheringGetUDKVersionString GetDeviceNameConstant Bus GetBusTypeGetMaxTransferSize Close Using devicesOpen Void ceDeviceOpenReadBlock ReadRegisterWriteRegister WriteBlockResetFPGA EnableInterruptWaitForInterrupt ProgramFPGAFromMemory SetTimeOutProgramFPGAFromBIN ProgramFPGAFromMemoryZEnableBurst Void ceDeviceEnableBurstbool bEnableUDKLab IntroductionMain screen UDKLab Main ScreenUsing UDKLab Device selection flowFpga configuration Prepare to work with deviceFpga design flashing ProjectsSequence contents Add new initializing task Content panel Sequence startRegister entry Register panelData area entry Data area panelUsing SPI-Flash for configuration How to store configuration data in SPI-FlashM25P16 Fpga Connection Jtag Signal Name Net name IO pairing and etch length reportJ3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT Direction52.506 Etch Length mm B18 J4 IDC-50 pin connector Differential pairs 17 IN/OUT Direction Fpga Bank Etch Length mm A28Addio 42.990 Mechanical dimensions USBS6 mechanical dimensions in mmTable of contents Table of Contents USB PCI ++ API