Company X Accessories C1030-5510 External expansion connectors, USB to serial Uart interface

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HEX rotary DIP switch

DIAL	FPGA Pin N8	FPGA Pin M11	FPGA Pin M10	FPGA Pin N9

5	0	1	0	1
6	1	0	0	1
7	0	0	0	1
8	1	1	1	0
9	0	1	1	0
A	1	0	1	0
B	0	0	1	0
C	1	1	0	0
D	0	1	0	0
E	1	0	0	0
F	0	0	0	0

FT232R from FTDI is a USB to serial UART interface.

USB to serial UART interface

Signal Name	FPGA IO	Direction	Comment
FTDI_TXD	U15	FPGA IN	Transmit asynchronous data output for FT232R.
FTDI_RXD	V15	FPGA OUT	Receiving asynchronous data input for FT232R.
FTDI_RTS_n	N11	FPGA IN	Request to send control output for FT232R.
FTDI_CTS_n	M8	FPGA OUT	Clear to send control input for FT232R.
FTDI_RESET_n	T12	FPGA OUT	Active low reset pin for FT232R.

External expansion connectors

On connectors J3 and J4 up to 115 general purpose FPGA IO are accessible. Bank 0 and Bank 3 of the FPGA are configured for 3.3V signaling level. Differential IO standards as for example LVDS are supported too. Detail information about IO pairing is available in paragraph IO pairing and etch length report of chapter D.

!IO on connectors J3 and J4 are directly connected to FPGA IO and therefore are only 3.3 Volt tolerant. NEVER apply voltages outside the interval [-0.95V..4.1V] as this may lead to severe damage of FPGA and attached components. For more information regarding DC and switching characteristics of Spartan-6 FPGA please consult documentation DS160 on XILINXTM website

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-13-	preliminary

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Contents June 29 USBS6Copyright information Summary of USBS6 Feature listIncluded in delivery XC6SLX16-2CSG324C Fpga features Block DiagramSpartan-6TMFPGA USBS6 Top View Bus- powered USB is used as power supply input 3V@ ??? mA Powering USBS6Modes of operation ModeJtag connector ConfigurationName USB2.0 controller Signal NameUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A Lpddr Sdram MT46H64M16LFCK-5 External memoryMCB1DQ0 SPI Flash MX25L12845EMI-10G PeripheralsLEDs HEX rotary DIP switchFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 USB to serial Uart interface External expansion connectorsDirection Comment J3 VG 96-pin external expansion connector J4 IDC 2x25-Pin external expansion connector IDC 2x25-Pin external expansion connector J4ADDIO16 Clocking Fpga designs Cypress FX-2 LP and USB basicsIntroduction to example Fpga designs FX-2/FPGA slave Fifo connectionISE Generate Programming File Properties Gen. Opt Fpga source code copyright information Disclaimer of warrantyFpga source code license Files and modules Design usbs6socSrc/wishbonepkg.vhd Src/wbintercon.vhd Src/usbs6soctop.vhdSrc/wbmafx2.vhd Src/wbslbram.vhdSrc/wbsluart.vhd Src/wbslmcb.vhdSrc/xiluartmacro Src/xilmcbmigSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by slaves Wishbone signals driven by the masterExample Design usbs6bramSrc/simtb/wbslbramtb.vhd Src/usbs6bramtop.vhdUsbs6bram.xise Usbs6bram.ucfWbslbramtb.cmd Changes to previous versions IntroductionWindows Driver installationRequirements Build UDKLets assume to use c\\udkapi Drivers LinuxPCI Makefile creation and build Preliminary Add project to UDK build Use APIs in own projectsAPI Functions in detail API Error handling++ and .NET API Error code Kind of error GetLastErrorCodeGetLastErrorText Methods/FunctionsInit Device enumerationDeInit DeviceType Description EnumerateGetDeviceCount Static unsigned int ceDeviceGetDeviceCountStatic ceDevice *ceDeviceGetDeviceunsigned int uiIdx GetDeviceGetUDKVersionString Information gatheringGetDeviceUID GetDeviceNameConstant Bus GetBusTypeGetMaxTransferSize Open Using devicesClose Void ceDeviceOpenWriteRegister ReadRegisterReadBlock WriteBlockResetFPGA EnableInterruptWaitForInterrupt ProgramFPGAFromBIN SetTimeOutProgramFPGAFromMemory ProgramFPGAFromMemoryZVoid ceDeviceEnableBurstbool bEnable EnableBurstIntroduction UDKLabUDKLab Main Screen Main screenDevice selection flow Using UDKLabPrepare to work with device Fpga configurationProjects Fpga design flashingSequence contents Add new initializing task Sequence start Content panelRegister panel Register entryData area panel Data area entryHow to store configuration data in SPI-Flash Using SPI-Flash for configurationM25P16 Fpga Connection Jtag Signal Name J3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT IO pairing and etch length reportNet name Direction52.506 Etch Length mm B18 Direction Fpga Bank Etch Length mm A28 J4 IDC-50 pin connector Differential pairs 17 IN/OUTAddio 42.990 USBS6 mechanical dimensions in mm Mechanical dimensionsTable of contents Table of Contents USB PCI ++ API