Company X Accessories C1030-5510 manual Configuration, Jtag connector, Name

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!It is strongly recommended to check XILINXTM UG381 about Spartan-6 FPGA SelectIO Signal Standards on XILINXTM website.

Configuration

Configuration of USBS6 can be accomplished in several ways: JTAG, SPI-Flash or USB. The default configuration mode is booting from SPI-Flash. After powering on the FPGA, USBS6 always tries to configure itself from the attached Flash using SPI Master mode. If no valid design is stored in the SPI-Flash the FPGA has to be configured via JTAG or USB. JTAG configuration is supported at any time after the FPGA is properly powered on. For downloading designs via JTAG ISE WebPACK from XILINXTM is recommended. The tool can be downloaded from XILINX web page free of charge. As JTAG connector USBS6 implements a standard 2x7-Pin header with 2mm pitch which is compatible to recent XILINXTM platform cables.

Figure 3: JTAG connector J2

J2	JTAG connector
PIN	Signal	FPGA	Comment	PIN	Signal	FPGA	Comment
	Name	IO			Name	IO
1	GND	--	Ground signal	2	VCCAUX	--	3.3V auxiliary supply.
3	GND	--	Ground signal	4	TMS	B18	Test Mode Select.
5	GND	--	Ground signal	6	TCK	A17	Test Clock.
7	GND	--	Ground signal	8	TDO	D16	Test Data Out.
9	GND	--	Ground signal	10	TDI	D15	Test Data In.
11	GND	--	Ground signal	12	--	--	No connection.
13	GND	--	Ground signal	14	--	--	No connection.

For further information on the different configuration solutions for XILINXTM SPARTAN-6TM

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-7-	preliminary

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Contents June 29 USBS6Copyright information Summary of USBS6 Feature listIncluded in delivery XC6SLX16-2CSG324C Fpga features Block DiagramSpartan-6TMFPGA USBS6 Top View Mode Powering USBS6Bus- powered USB is used as power supply input 3V@ ??? mA Modes of operationJtag connector ConfigurationName USB2.0 controller Signal NameUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A Lpddr Sdram MT46H64M16LFCK-5 External memoryMCB1DQ0 SPI Flash MX25L12845EMI-10G PeripheralsLEDs HEX rotary DIP switchFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 USB to serial Uart interface External expansion connectorsDirection Comment J3 VG 96-pin external expansion connector J4 IDC 2x25-Pin external expansion connector IDC 2x25-Pin external expansion connector J4ADDIO16 Clocking Fpga designs Cypress FX-2 LP and USB basicsIntroduction to example Fpga designs FX-2/FPGA slave Fifo connectionISE Generate Programming File Properties Gen. Opt Fpga source code copyright information Disclaimer of warrantyFpga source code license Files and modules Design usbs6socSrc/wishbonepkg.vhd Src/wbslbram.vhd Src/usbs6soctop.vhdSrc/wbintercon.vhd Src/wbmafx2.vhdSrc/xilmcbmig Src/wbslmcb.vhdSrc/wbsluart.vhd Src/xiluartmacroSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by slaves Wishbone signals driven by the masterExample Design usbs6bramUsbs6bram.ucf Src/usbs6bramtop.vhdSrc/simtb/wbslbramtb.vhd Usbs6bram.xiseWbslbramtb.cmd Changes to previous versions IntroductionBuild UDK Driver installationWindows RequirementsLets assume to use c\\udkapi Drivers LinuxPCI Makefile creation and build Preliminary Add project to UDK build Use APIs in own projectsAPI Functions in detail API Error handling++ and .NET API Methods/Functions GetLastErrorCodeError code Kind of error GetLastErrorTextInit Device enumerationDeInit Static unsigned int ceDeviceGetDeviceCount EnumerateDeviceType Description GetDeviceCountStatic ceDevice *ceDeviceGetDeviceunsigned int uiIdx GetDeviceGetDeviceName Information gatheringGetUDKVersionString GetDeviceUIDConstant Bus GetBusTypeGetMaxTransferSize Void ceDeviceOpen Using devicesOpen CloseWriteBlock ReadRegisterWriteRegister ReadBlockResetFPGA EnableInterruptWaitForInterrupt ProgramFPGAFromMemoryZ SetTimeOutProgramFPGAFromBIN ProgramFPGAFromMemoryVoid ceDeviceEnableBurstbool bEnable EnableBurstIntroduction UDKLabUDKLab Main Screen Main screenDevice selection flow Using UDKLabPrepare to work with device Fpga configurationProjects Fpga design flashingSequence contents Add new initializing task Sequence start Content panelRegister panel Register entryData area panel Data area entryHow to store configuration data in SPI-Flash Using SPI-Flash for configurationM25P16 Fpga Connection Jtag Signal Name Direction IO pairing and etch length reportJ3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT Net name52.506 Etch Length mm B18 Direction Fpga Bank Etch Length mm A28 J4 IDC-50 pin connector Differential pairs 17 IN/OUTAddio 42.990 USBS6 mechanical dimensions in mm Mechanical dimensionsTable of contents Table of Contents USB PCI ++ API