Company X Accessories C1030-5510 manual Powering USBS6, Modes of operation, Comment

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Powering USBS6

USBS6 may be used bus-powered (see SW2 below) without the need of any external power supply other than USB. In this mode VCCO_IO on J3,PIN A3, B3, C3 sourcing capability is limited due to the fact, that USB power supply current is limited depending on which system is used as host. Typically USB hosts allow up to 500mA. In bus-powered mode, at first only FX2 is enabled. After successful connection to the operating system the further power-on sequencing behavior depends on UDK configuration. Until the release of UDK2.0 only the API could enable further power-on sequencing, therefore after plugging an USB cable it also was necessary to start an application like cesys- Monitor before the FPGA and other devices turned on. With v2.0 and upcoming releases of UDK framework the user now can decide which power-on behavior fits best. Power-on sequencing through API or as soon as USB cable is plugged in. Default mode is API- controlled.

Modes of operation

Mode

SW2

Comment *

VCCO_IO

Bus- powered

 

USB is used as power supply input.

3.3V@ ??? mA

 

 

 

 

Self- powered

Connect 5V power supply to VG- 96pin external expansion connector J3 PINS A1, B1 and C1.

3.3V@ 3 A **

Minimum required supply current: ???A

*The actual required supply current strongly depends on FGPA design and may exceed the minimum required.

**In self-powered mode the actual VCCO_IO current limit depends on sourcing capability of external 5V power supply and may be less.

If the attached USB2.0 host interface should not be used as power supply, it is possible to use USBS6 self-powered (see SW2 above). In this mode an external 5V power supply must be connected to the external expansion connector J3, PINS A1, B1 and C1. All onboard voltages are enabled as soon as an external power supply is applied. VCCO on BANK0 and BANK3 is tied together to VCCO_IO but routed independent from other supply voltages. Therefore in self-powered mode maximum current available on J3,PIN

A3, B3, C3 (VCCO_IO) mainly depends on the external power supply to the limit of the onboard regulator, which is about 3A. As default VCCO_IO is regulated to 3.3V to enable 3.3V signaling levels on the external expansion connectors. Other signaling levels may be supported but require adjustment of the onboard synchronous buck regulator to the desired value.

USBS6 / C1030-5510

 

http://www.cesys.com/

User Doc V0.3

-6-

preliminary

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Contents USBS6 June 29Copyright information Feature list Summary of USBS6Included in delivery Block Diagram XC6SLX16-2CSG324C Fpga featuresSpartan-6TMFPGA USBS6 Top View Modes of operation Powering USBS6Bus- powered USB is used as power supply input 3V@ ??? mA ModeConfiguration Jtag connectorName Signal Name USB2.0 controllerUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A External memory Lpddr Sdram MT46H64M16LFCK-5MCB1DQ0 Peripherals SPI Flash MX25L12845EMI-10GHEX rotary DIP switch LEDsFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 External expansion connectors USB to serial Uart interfaceDirection Comment J3 VG 96-pin external expansion connector IDC 2x25-Pin external expansion connector J4 J4 IDC 2x25-Pin external expansion connectorADDIO16 Cypress FX-2 LP and USB basics Clocking Fpga designsFX-2/FPGA slave Fifo connection Introduction to example Fpga designsISE Generate Programming File Properties Gen. Opt Disclaimer of warranty Fpga source code copyright informationFpga source code license Design usbs6soc Files and modulesSrc/wishbonepkg.vhd Src/wbmafx2.vhd Src/usbs6soctop.vhdSrc/wbintercon.vhd Src/wbslbram.vhdSrc/xiluartmacro Src/wbslmcb.vhdSrc/wbsluart.vhd Src/xilmcbmigSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by the master Wishbone signals driven by slavesDesign usbs6bram ExampleUsbs6bram.xise Src/usbs6bramtop.vhdSrc/simtb/wbslbramtb.vhd Usbs6bram.ucfWbslbramtb.cmd Introduction Changes to previous versionsRequirements Driver installationWindows Build UDKLets assume to use c\\udkapi Linux DriversPCI Makefile creation and build Preliminary Use APIs in own projects Add project to UDK buildAPI Error handling API Functions in detail++ and .NET API GetLastErrorText GetLastErrorCodeError code Kind of error Methods/FunctionsDevice enumeration InitDeInit GetDeviceCount EnumerateDeviceType Description Static unsigned int ceDeviceGetDeviceCountGetDevice Static ceDevice *ceDeviceGetDeviceunsigned int uiIdxGetDeviceUID Information gatheringGetUDKVersionString GetDeviceNameGetBusType Constant BusGetMaxTransferSize Close Using devicesOpen Void ceDeviceOpenReadBlock ReadRegisterWriteRegister WriteBlockEnableInterrupt ResetFPGAWaitForInterrupt ProgramFPGAFromMemory SetTimeOutProgramFPGAFromBIN ProgramFPGAFromMemoryZEnableBurst Void ceDeviceEnableBurstbool bEnableUDKLab IntroductionMain screen UDKLab Main ScreenUsing UDKLab Device selection flowFpga configuration Prepare to work with deviceFpga design flashing ProjectsSequence contents Add new initializing task Content panel Sequence startRegister entry Register panelData area entry Data area panelUsing SPI-Flash for configuration How to store configuration data in SPI-FlashM25P16 Fpga Connection Jtag Signal Name Net name IO pairing and etch length reportJ3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT Direction52.506 Etch Length mm B18 J4 IDC-50 pin connector Differential pairs 17 IN/OUT Direction Fpga Bank Etch Length mm A28Addio 42.990 Mechanical dimensions USBS6 mechanical dimensions in mmTable of contents Table of Contents USB PCI ++ API
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