Company X Accessories C1030-5510 manual Src/wbslmcb.vhd, Src/wbsluart.vhd, Src/xiluartmacro

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programming FPGA configuration bitstream to SPI-FLASH and the other accesses QUAD- SPI-FLASH for storing nonvolatile application data.

src/wb_sl_mcb.vhd:

WISHBONE adapter for one port of Spartan-6TMbuild in multiport memory controller block (MCB).

src/wb_sl_uart.vhd:

This entity is a simple UART transceiver with 16 byte buffer for each direction connected to USB2UART interface. XilinxTM UART transceiver macros are used as physical layer. Baudrate is adjustable up to 230400 (default: 9600) by writing appropriate timer prescaling values to the status and configuration register. This register contains buffer level flags FULL and HALFFULL for each direction, too. Data format is fixed at 8-N-1. Reading from UART pipe is always non-blocking. A data present flag provided along with received bytes indicates, if current RX value is valid. Writing to UART pipe is blocking, if TX buffer gets full. So that loss of transmitted data can easily be avoided.

src/xil_uart_macro/:

This directory contains VHDL source code files of XilinxTM UART transceiver macros. Note that these source code files are copyrighted by XilinxTM and are absolutely not supported by CESYS! For details on these macros see the application note “XAPP223 - 200 MHz UART with Internal 16-Byte Buffer” provided by XilinxTM.

src/xil_mcb_mig/:

This directory contains VHDL source code files generated by XilinxTM memory interface generator tool to build the frontend for MCB. File memc1_infrastructure.vhd has been modified to fit example design requirements.

src/fx2_slfifo_ctrl.vhd:

This controller handles 512 byte aligned raw USB bulk transfers without CESYS USB transfer protocol. It checks FX-2 FIFO flags and copies data from FX-2 endpoints to internal FPGA buffers (sync_fifo.vhd) and vice versa. So the USB data link looks like any other FPGA FIFO buffer to user logic. Ports of fx2_slfifo_ctrl connected to FX-2 are labeled with prefix fx2_ and ports connected to user logic are labeled with prefix app_. Sometimes the abbreviations _h2p_ (host to peripheral) and _p2h_ (peripheral to host) are used in signal names to indicate data flow direction.

USBS6 / C1030-5510

 

http://www.cesys.com/

User Doc V0.3

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preliminary

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Contents June 29 USBS6Copyright information Included in delivery Feature listSummary of USBS6 Spartan-6TMFPGA Block DiagramXC6SLX16-2CSG324C Fpga features USBS6 Top View Mode Powering USBS6Bus- powered USB is used as power supply input 3V@ ??? mA Modes of operationName ConfigurationJtag connector USB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A Signal NameUSB2.0 controller Lpddr Sdram MT46H64M16LFCK-5 External memoryMCB1DQ0 SPI Flash MX25L12845EMI-10G PeripheralsFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 HEX rotary DIP switchLEDs Direction Comment External expansion connectorsUSB to serial Uart interface J3 VG 96-pin external expansion connector J4 IDC 2x25-Pin external expansion connector IDC 2x25-Pin external expansion connector J4ADDIO16 Clocking Fpga designs Cypress FX-2 LP and USB basicsIntroduction to example Fpga designs FX-2/FPGA slave Fifo connectionISE Generate Programming File Properties Gen. Opt Fpga source code license Disclaimer of warrantyFpga source code copyright information Src/wishbonepkg.vhd Design usbs6socFiles and modules Src/wbslbram.vhd Src/usbs6soctop.vhdSrc/wbintercon.vhd Src/wbmafx2.vhdSrc/xilmcbmig Src/wbslmcb.vhdSrc/wbsluart.vhd Src/xiluartmacroSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by slaves Wishbone signals driven by the masterExample Design usbs6bramUsbs6bram.ucf Src/usbs6bramtop.vhdSrc/simtb/wbslbramtb.vhd Usbs6bram.xiseWbslbramtb.cmd Changes to previous versions IntroductionBuild UDK Driver installationWindows RequirementsLets assume to use c\\udkapi Drivers LinuxPCI Makefile creation and build Preliminary Add project to UDK build Use APIs in own projects++ and .NET API API Error handlingAPI Functions in detail Methods/Functions GetLastErrorCodeError code Kind of error GetLastErrorTextDeInit Device enumerationInit Static unsigned int ceDeviceGetDeviceCount EnumerateDeviceType Description GetDeviceCountStatic ceDevice *ceDeviceGetDeviceunsigned int uiIdx GetDeviceGetDeviceName Information gatheringGetUDKVersionString GetDeviceUIDGetMaxTransferSize GetBusTypeConstant Bus Void ceDeviceOpen Using devicesOpen CloseWriteBlock ReadRegisterWriteRegister ReadBlockWaitForInterrupt EnableInterruptResetFPGA ProgramFPGAFromMemoryZ SetTimeOutProgramFPGAFromBIN ProgramFPGAFromMemoryVoid ceDeviceEnableBurstbool bEnable EnableBurstIntroduction UDKLabUDKLab Main Screen Main screenDevice selection flow Using UDKLabPrepare to work with device Fpga configurationProjects Fpga design flashingSequence contents Add new initializing task Sequence start Content panelRegister panel Register entryData area panel Data area entryHow to store configuration data in SPI-Flash Using SPI-Flash for configurationM25P16 Fpga Connection Jtag Signal Name Direction IO pairing and etch length reportJ3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT Net name52.506 Etch Length mm B18 Direction Fpga Bank Etch Length mm A28 J4 IDC-50 pin connector Differential pairs 17 IN/OUTAddio 42.990 USBS6 mechanical dimensions in mm Mechanical dimensionsTable of contents Table of Contents USB PCI ++ API