Company X Accessories C1030-5510 manual 52.506

Page 63

PIN	Net name	FPGA IO	P / N	Direction	FPGA BANK	Etch Length (mm)
A11	VG96_IO21	F2	P	IN	BANK 3	52.506
B11	VG96_IO22	F1	N	IN	BANK 3	52.504

C11	VG96_IO23	J3	P	IN	BANK 3	60.987
C10	VG96_IO20	J1	N	IN	BANK 3	60.972

A12	VG96_IO24	D2	P	IN	BANK 3	50.233
B12	VG96_IO25	D1	N	IN	BANK 3	50.221

A13	VG96_IO27	C2	P	IN	BANK 3	48.317
B13	VG96_IO28	C1	N	IN	BANK 3	48.315

C13	VG96_IO29	G3	P	IN	BANK 3	62.860
C12	VG96_IO26	G1	N	IN	BANK 3	62.840

A14	VG96_IO30	L4	P	IN	BANK 3	61.467
B14	VG96_IO31	L3	N	IN	BANK 3	61.456

A15	VG96_IO33	L5	P	IN	BANK 3	62.236
B15	VG96_IO34	K5	N	IN	BANK 3	62.210

C15	VG96_IO35	E3	P	IN	BANK 3	65.015
C14	VG96_IO32	E1	N	IN	BANK 3	65.008

A16	VG96_IO36	L7	P	IN	BANK 3	64.049
B16	VG96_IO37	K6	N	IN	BANK 3	63.853

A17	VG96_IO39	K4	P	IN	BANK 3	67.057
B17	VG96_IO40	K3	N	IN	BANK 3	67.031

C17	VG96_IO41	L6	P	IN	BANK 3	62.885
C16	VG96_IO38	M5	N	IN	BANK 3	62.926

A18

VG96_IO42

H6

P

IN

BANK 3

63.499

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-63-	preliminary

Image 63

Contents June 29 USBS6Copyright information Feature list Summary of USBS6Included in delivery Block Diagram XC6SLX16-2CSG324C Fpga featuresSpartan-6TMFPGA USBS6 Top View Mode Powering USBS6Bus- powered USB is used as power supply input 3V@ ??? mA Modes of operationConfiguration Jtag connectorName Signal Name USB2.0 controllerUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A Lpddr Sdram MT46H64M16LFCK-5 External memoryMCB1DQ0 SPI Flash MX25L12845EMI-10G PeripheralsHEX rotary DIP switch LEDsFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 External expansion connectors USB to serial Uart interfaceDirection Comment J3 VG 96-pin external expansion connector J4 IDC 2x25-Pin external expansion connector IDC 2x25-Pin external expansion connector J4ADDIO16 Clocking Fpga designs Cypress FX-2 LP and USB basicsIntroduction to example Fpga designs FX-2/FPGA slave Fifo connectionISE Generate Programming File Properties Gen. Opt Disclaimer of warranty Fpga source code copyright informationFpga source code license Design usbs6soc Files and modulesSrc/wishbonepkg.vhd Src/wbslbram.vhd Src/usbs6soctop.vhdSrc/wbintercon.vhd Src/wbmafx2.vhdSrc/xilmcbmig Src/wbslmcb.vhdSrc/wbsluart.vhd Src/xiluartmacroSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by slaves Wishbone signals driven by the masterExample Design usbs6bramUsbs6bram.ucf Src/usbs6bramtop.vhdSrc/simtb/wbslbramtb.vhd Usbs6bram.xiseWbslbramtb.cmd Changes to previous versions IntroductionBuild UDK Driver installationWindows RequirementsLets assume to use c\\udkapi Drivers LinuxPCI Makefile creation and build Preliminary Add project to UDK build Use APIs in own projectsAPI Error handling API Functions in detail++ and .NET API Methods/Functions GetLastErrorCodeError code Kind of error GetLastErrorTextDevice enumeration InitDeInit Static unsigned int ceDeviceGetDeviceCount EnumerateDeviceType Description GetDeviceCountStatic ceDevice *ceDeviceGetDeviceunsigned int uiIdx GetDeviceGetDeviceName Information gatheringGetUDKVersionString GetDeviceUIDGetBusType Constant BusGetMaxTransferSize Void ceDeviceOpen Using devicesOpen CloseWriteBlock ReadRegisterWriteRegister ReadBlockEnableInterrupt ResetFPGAWaitForInterrupt ProgramFPGAFromMemoryZ SetTimeOutProgramFPGAFromBIN ProgramFPGAFromMemoryVoid ceDeviceEnableBurstbool bEnable EnableBurstIntroduction UDKLabUDKLab Main Screen Main screenDevice selection flow Using UDKLabPrepare to work with device Fpga configurationProjects Fpga design flashingSequence contents Add new initializing task Sequence start Content panelRegister panel Register entryData area panel Data area entryHow to store configuration data in SPI-Flash Using SPI-Flash for configurationM25P16 Fpga Connection Jtag Signal Name Direction IO pairing and etch length reportJ3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT Net name52.506 Etch Length mm B18 Direction Fpga Bank Etch Length mm A28 J4 IDC-50 pin connector Differential pairs 17 IN/OUTAddio 42.990 USBS6 mechanical dimensions in mm Mechanical dimensionsTable of contents Table of Contents USB PCI ++ API