Company X Accessories C1030-5510 manual Sequence start, Content panel

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Sequence start

The button sitting below the list runs all actions from top to bottom. In addition to this, the remaining UI components, the content panel, will be enabled, as UDKLab expects a working communication at this point. The sequence can be modified an started as often as wished.

Content panel

The content panel can be a visual representation of the FPGA design loaded during initialization. It consists of a list of registers and data areas, which can be visit and modified using UDKLab. The view is split into two columns, while the left part contains the registers and the right part all data area / block entries.

Figure 17: Content panel

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-57-	preliminary

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Contents June 29 USBS6Copyright information Feature list Summary of USBS6Included in delivery Block Diagram XC6SLX16-2CSG324C Fpga featuresSpartan-6TMFPGA USBS6 Top View Bus- powered USB is used as power supply input 3V@ ??? mA Powering USBS6Modes of operation ModeConfiguration Jtag connectorName Signal Name USB2.0 controllerUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A Lpddr Sdram MT46H64M16LFCK-5 External memoryMCB1DQ0 SPI Flash MX25L12845EMI-10G PeripheralsHEX rotary DIP switch LEDsFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 External expansion connectors USB to serial Uart interfaceDirection Comment J3 VG 96-pin external expansion connector J4 IDC 2x25-Pin external expansion connector IDC 2x25-Pin external expansion connector J4ADDIO16 Clocking Fpga designs Cypress FX-2 LP and USB basicsIntroduction to example Fpga designs FX-2/FPGA slave Fifo connectionISE Generate Programming File Properties Gen. Opt Disclaimer of warranty Fpga source code copyright informationFpga source code license Design usbs6soc Files and modulesSrc/wishbonepkg.vhd Src/wbintercon.vhd Src/usbs6soctop.vhdSrc/wbmafx2.vhd Src/wbslbram.vhdSrc/wbsluart.vhd Src/wbslmcb.vhdSrc/xiluartmacro Src/xilmcbmigSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by slaves Wishbone signals driven by the masterExample Design usbs6bramSrc/simtb/wbslbramtb.vhd Src/usbs6bramtop.vhdUsbs6bram.xise Usbs6bram.ucfWbslbramtb.cmd Changes to previous versions IntroductionWindows Driver installationRequirements Build UDKLets assume to use c\\udkapi Drivers LinuxPCI Makefile creation and build Preliminary Add project to UDK build Use APIs in own projectsAPI Error handling API Functions in detail++ and .NET API Error code Kind of error GetLastErrorCodeGetLastErrorText Methods/FunctionsDevice enumeration InitDeInit DeviceType Description EnumerateGetDeviceCount Static unsigned int ceDeviceGetDeviceCountStatic ceDevice *ceDeviceGetDeviceunsigned int uiIdx GetDeviceGetUDKVersionString Information gatheringGetDeviceUID GetDeviceNameGetBusType Constant BusGetMaxTransferSize Open Using devicesClose Void ceDeviceOpenWriteRegister ReadRegisterReadBlock WriteBlockEnableInterrupt ResetFPGAWaitForInterrupt ProgramFPGAFromBIN SetTimeOutProgramFPGAFromMemory ProgramFPGAFromMemoryZVoid ceDeviceEnableBurstbool bEnable EnableBurstIntroduction UDKLabUDKLab Main Screen Main screenDevice selection flow Using UDKLabPrepare to work with device Fpga configurationProjects Fpga design flashingSequence contents Add new initializing task Sequence start Content panelRegister panel Register entryData area panel Data area entryHow to store configuration data in SPI-Flash Using SPI-Flash for configurationM25P16 Fpga Connection Jtag Signal Name J3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT IO pairing and etch length reportNet name Direction52.506 Etch Length mm B18 Direction Fpga Bank Etch Length mm A28 J4 IDC-50 pin connector Differential pairs 17 IN/OUTAddio 42.990 USBS6 mechanical dimensions in mm Mechanical dimensionsTable of contents Table of Contents USB PCI ++ API