Company X Accessories C1030-5510 manual ISE Generate Programming File Properties Gen. Opt

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VHDL. Verilog and schematic entry design flows are not supported.

•The design “usbs6_soc” demonstrates the implementation of a system-on-chip (SoC) with host software access to the peripherals like GPIOs, external Flash Memory, LPDDR Memory and internal BlockRAM over USB. This design requires a protocol layer over the simple USB bulk transfer (see CESYS application note “Transfer Protocol for CESYS USB products” for details), which is already provided by CESYS software API.

•The design “usbs6_bram” is a minimal example for data transfers from and to the FPGA over USB and can be used to get for familiar with UDK hardware/software interface.

The Spartan-6 XC6SLX16 Device is supported by the free XilinxTM ISE Webpack development software. You will have to change some options of the project properties for own applications.

A bitstream in the “*.bin”-format is needed, if you want to download your FPGA design with the CESYS software API-functions LoadBIN() and ProgramFPGA(). The generation of this file is disabled by default in the XilinxTM ISE development environment. Check “create binary configuration file” at right click “generate programming file”=>properties=>general options:

Figure 7: ISE Generate Programming File Properties (Gen. Opt.)

USBS6 / C1030-5510		http://www.cesys.com/
User Doc V0.3	-19-	preliminary

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Contents June 29 USBS6Copyright information Summary of USBS6 Feature listIncluded in delivery XC6SLX16-2CSG324C Fpga features Block DiagramSpartan-6TMFPGA USBS6 Top View Mode Powering USBS6Bus- powered USB is used as power supply input 3V@ ??? mA Modes of operationJtag connector ConfigurationName USB2.0 controller Signal NameUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A Lpddr Sdram MT46H64M16LFCK-5 External memoryMCB1DQ0 SPI Flash MX25L12845EMI-10G PeripheralsLEDs HEX rotary DIP switchFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 USB to serial Uart interface External expansion connectorsDirection Comment J3 VG 96-pin external expansion connector J4 IDC 2x25-Pin external expansion connector IDC 2x25-Pin external expansion connector J4ADDIO16 Clocking Fpga designs Cypress FX-2 LP and USB basicsIntroduction to example Fpga designs FX-2/FPGA slave Fifo connectionISE Generate Programming File Properties Gen. Opt Fpga source code copyright information Disclaimer of warrantyFpga source code license Files and modules Design usbs6socSrc/wishbonepkg.vhd Src/wbslbram.vhd Src/usbs6soctop.vhdSrc/wbintercon.vhd Src/wbmafx2.vhdSrc/xilmcbmig Src/wbslmcb.vhdSrc/wbsluart.vhd Src/xiluartmacroSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by slaves Wishbone signals driven by the masterExample Design usbs6bramUsbs6bram.ucf Src/usbs6bramtop.vhdSrc/simtb/wbslbramtb.vhd Usbs6bram.xiseWbslbramtb.cmd Changes to previous versions IntroductionBuild UDK Driver installationWindows RequirementsLets assume to use c\\udkapi Drivers LinuxPCI Makefile creation and build Preliminary Add project to UDK build Use APIs in own projectsAPI Functions in detail API Error handling++ and .NET API Methods/Functions GetLastErrorCodeError code Kind of error GetLastErrorTextInit Device enumerationDeInit Static unsigned int ceDeviceGetDeviceCount EnumerateDeviceType Description GetDeviceCountStatic ceDevice *ceDeviceGetDeviceunsigned int uiIdx GetDeviceGetDeviceName Information gatheringGetUDKVersionString GetDeviceUIDConstant Bus GetBusTypeGetMaxTransferSize Void ceDeviceOpen Using devicesOpen CloseWriteBlock ReadRegisterWriteRegister ReadBlockResetFPGA EnableInterruptWaitForInterrupt ProgramFPGAFromMemoryZ SetTimeOutProgramFPGAFromBIN ProgramFPGAFromMemoryVoid ceDeviceEnableBurstbool bEnable EnableBurstIntroduction UDKLabUDKLab Main Screen Main screenDevice selection flow Using UDKLabPrepare to work with device Fpga configurationProjects Fpga design flashingSequence contents Add new initializing task Sequence start Content panelRegister panel Register entryData area panel Data area entryHow to store configuration data in SPI-Flash Using SPI-Flash for configurationM25P16 Fpga Connection Jtag Signal Name Direction IO pairing and etch length reportJ3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT Net name52.506 Etch Length mm B18 Direction Fpga Bank Etch Length mm A28 J4 IDC-50 pin connector Differential pairs 17 IN/OUTAddio 42.990 USBS6 mechanical dimensions in mm Mechanical dimensionsTable of contents Table of Contents USB PCI ++ API