Company X Accessories C1030-5510 manual IDC 2x25-Pin external expansion connector J4

Page 15

J3 VG 96-pin external expansion connector

PIN

FPGA

Comment

PIN

FPGA

Comment

PIN

FPGA

Comment

 

IO

 

 

IO

 

 

IO

 

A7

N2

VG96_IO9

B7

N1

VG96_IO10

C7

N4

VG96_IO11

A6

P2

VG96_IO6

B6

P1

VG96_IO7

C6

N3

VG96_IO8

A5

T2

VG96_IO3

B5

T1

VG96_IO4

C5

P4

VG96_IO5

A4

U2

VG96_IO0

B4

U1

VG96_IO1

C4

P3

VG96_IO2

A3

--

VCCO_IO

B3

--

VCCO_IO

C3

--

VCCO_IO

A2

--

GND

B2

--

GND

C2

--

GND

A1

--

5.0V_EXT

B1

--

5.0V_EXT

C1

--

5.0V_EXT

* GCLK

Figure 6: IDC 2x25-Pin external expansion connector J4

 

J4 IDC 2x25-Pin external expansion connector

 

 

 

PIN

FPGA IO

Comment

 

PIN

FPGA IO

Comment

 

 

1

--

VCCO_IO

 

2

--

GND

 

 

3

C5

ADD_IO0

 

4

A5

ADD_IO1

 

 

5

C7

ADD_IO2

 

6

A7

ADD_IO3

 

 

7

--

GND

 

8

--

GND

 

 

9

B2

ADD_IO4

 

10

A2

ADD_IO5

 

 

11

B3

ADD_IO6

 

12

A3

ADD_IO7

 

 

13

B4

ADD_IO8

 

14

A4

ADD_IO9

 

 

15

B6

ADD_IO10

 

16

A6

ADD_IO11

 

 

17

--

GND

 

18

--

GND

 

 

19

B8

ADD_IO12

 

20

A8

ADD_IO13

 

 

21

B9

ADD_IO14*

 

22

A9

ADD_IO15*

 

 

23

--

GND

 

24

--

GND

 

 

 

 

 

 

 

 

 

USBS6 / C1030-5510

 

 

 

 

http://www.cesys.com/

User Doc V0.3

 

-15-

 

preliminary

Image 15
Contents June 29 USBS6Copyright information Feature list Summary of USBS6Included in delivery Block Diagram XC6SLX16-2CSG324C Fpga featuresSpartan-6TMFPGA USBS6 Top View Mode Powering USBS6Bus- powered USB is used as power supply input 3V@ ??? mA Modes of operationConfiguration Jtag connectorName Signal Name USB2.0 controllerUSB2.0 FX2LPTM Microcontroller Cypresstm CY7C68013A Lpddr Sdram MT46H64M16LFCK-5 External memoryMCB1DQ0 SPI Flash MX25L12845EMI-10G PeripheralsHEX rotary DIP switch LEDsFpga Pin N8 Fpga Pin M11 Fpga Pin M10 Fpga Pin N9 External expansion connectors USB to serial Uart interfaceDirection Comment J3 VG 96-pin external expansion connector J4 IDC 2x25-Pin external expansion connector IDC 2x25-Pin external expansion connector J4ADDIO16 Clocking Fpga designs Cypress FX-2 LP and USB basicsIntroduction to example Fpga designs FX-2/FPGA slave Fifo connectionISE Generate Programming File Properties Gen. Opt Disclaimer of warranty Fpga source code copyright informationFpga source code license Design usbs6soc Files and modulesSrc/wishbonepkg.vhd Src/wbslbram.vhd Src/usbs6soctop.vhdSrc/wbintercon.vhd Src/wbmafx2.vhdSrc/xilmcbmig Src/wbslmcb.vhdSrc/wbsluart.vhd Src/xiluartmacroSignals appusbh2ppktcounto70 and appusbp2hpktcounto70 Wishbone transactions Wishbone signals driven by slaves Wishbone signals driven by the masterExample Design usbs6bramUsbs6bram.ucf Src/usbs6bramtop.vhdSrc/simtb/wbslbramtb.vhd Usbs6bram.xiseWbslbramtb.cmd Changes to previous versions IntroductionBuild UDK Driver installationWindows RequirementsLets assume to use c\\udkapi Drivers LinuxPCI Makefile creation and build Preliminary Add project to UDK build Use APIs in own projectsAPI Error handling API Functions in detail++ and .NET API Methods/Functions GetLastErrorCodeError code Kind of error GetLastErrorTextDevice enumeration InitDeInit Static unsigned int ceDeviceGetDeviceCount EnumerateDeviceType Description GetDeviceCountStatic ceDevice *ceDeviceGetDeviceunsigned int uiIdx GetDeviceGetDeviceName Information gatheringGetUDKVersionString GetDeviceUIDGetBusType Constant BusGetMaxTransferSize Void ceDeviceOpen Using devicesOpen CloseWriteBlock ReadRegisterWriteRegister ReadBlockEnableInterrupt ResetFPGAWaitForInterrupt ProgramFPGAFromMemoryZ SetTimeOutProgramFPGAFromBIN ProgramFPGAFromMemoryVoid ceDeviceEnableBurstbool bEnable EnableBurstIntroduction UDKLabUDKLab Main Screen Main screenDevice selection flow Using UDKLabPrepare to work with device Fpga configurationProjects Fpga design flashingSequence contents Add new initializing task Sequence start Content panelRegister panel Register entryData area panel Data area entryHow to store configuration data in SPI-Flash Using SPI-Flash for configurationM25P16 Fpga Connection Jtag Signal Name Direction IO pairing and etch length reportJ3 VG-96 pin connector Differential pairs 28 IN, 12 IN/OUT Net name52.506 Etch Length mm B18 Direction Fpga Bank Etch Length mm A28 J4 IDC-50 pin connector Differential pairs 17 IN/OUTAddio 42.990 USBS6 mechanical dimensions in mm Mechanical dimensionsTable of contents Table of Contents USB PCI ++ API