User’s Guide 21020285 D
Chapter 2 Hardware Essentials
Hardware Structure and Description Page 2 - 3
Hardware Structure and Description
The RF3880 hardware design incorporates the technology available from the
following components:
• Intel 20 MHz 80186XL microprocessor
• QLogic FAS256 16-bit, Fast SCSI Controller chip
• High Density Programmable Logic Devices (PLD’s) for VMEbus, and
buffer control
• Ciprico Pipelined System Interface (PSI)
Intel 80186XL At the core of the RF3880 design is the 80186XL supervisory microprocessor.
The 80186 is well suited to the task of overseeing board operations; it uses
optimized instruction encoding for high performance and memory efficiency.
RF3880 performance is further boosted by using the 20 MHz version of the
80186.

QLogic

FAS 256

SCSI bus protocol for the RF3880 is efficiently handled by the QLogic Fast
SCSI chip. The QLogic chip provides the capability for 16-bit tr ansfers on the
SCSI bus, as well as negotiation for Fast Synchronous transfers across the bus,
up to 20 MB/s. The QLogic FAS256 chip is a registered device that can be se t-
up for automated bus operations. These options are available to you via the
Board-control commands discussed in Chapter 7.

Pipelined

System

Interface

Ciprico created the custom VLS I Pipelined System Interface (PSI) to
coordinate access to the system address bus; it has registers for the DMA
address count and transfer count. Also contained in the chip are the Channel
Attention port register and the Interrupt Request level register.
Data Buffer Using high-speed video DRAMs to provide 512 Kbytes of buffer space with
hardware control logic, the RF3880 creates a data buffer that adjusts
dynamically to the type and size of the data transfers involved. Performed in
hardware, this design maximizes performance by bypassing the need for
microprocessor involvement.