Fluke 2620A, 2625A user manual Service Request Enable Register, Instrument Event Register

Using the Computer Interface	4
General Information (RS-232 and IEEE-488)

Service Request Enable Register

The Service Request Enable Register (SRE) is an 8-bit register that enables or disables (i.e., masks) corresponding summary messages in the Status Byte Register (STB). The instrument can be programmed to make a service request on errors or when output is available. Conditions that trigger a service request are specified by writing a binary- weighted value to the Service Request Enable Register, using the *SRE command.

EXAMPLE EXPLANATION

*SRE	16Enables the generation of an SRQ when bit 4 (MAV) in the Status Byte
	Register (STB) is set to 1.
	16 is the decimal equivalent of 00010000 binary. This means that bit 4 in the
	Service Request Enable Register (SRE, which corresponds to the MAV bit
	in the Status ByteRegister) is 1, and all other bits are 0.

*SRE 48 Enables the generation of an SRQ when bits 4 or 5 (MAV or ESB) in the Status Byte Register are set to 1. The binary equivalent of 48 is 00110000, indicating that bits 4 and 5 are set to 1.

If any bit in the SRE is set to 1 and the matching bit(s) in the STB become 1, the RQS bit (bit 6) in the Status Byte Register (STB) is set and a service request can be generated.

Use the *SRE? query to read the Service Request Enable Register. The instrument returns a binary-weighted integer that represents the enabled bits in the register. (The value of bit 6 will always be zero.) Convert the returned value to binary to determine the status of register bits.

EXAMPLE EXPLANATION

*SRE?	Reads the value of the SRE Register. Assume "4" is returned. Converting 4
	to the binary 00000100 indicates that bit 2 in the SRE is set to 1.

Instrument Event Register

The Instrument Event Register (IER) is used in conjunction with the Instrument Event Enable Register (IEE) to determine the conditions under which the Instrument Event Bit of the Status Byte Register is set. Bits used in the Instrument Event Register are described in Table 4-6. Whenever the Instrument Event Register is read, the instrument bits are cleared.

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