Interface
after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and tRFS timing for the device.
5)The host shall assert STOP no sooner than tRP after negating
6)The device shall negate DMARQ within tLI after the host has asserted STOP. The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.
7)If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra DMA burst is terminated.
8)The device shall release DD (15:0) no later than tAZ after negating
DMARQ.
9)The host shall drive DD (15:0) no sooner than tZAH after the device has negated DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC calculation (see 5.5.5).
10)If the host has not placed the result of its CRC calculation on DD (15:0) since first driving DD (15:0) during (9), the host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5).
11)The host shall negate DMACK- no sooner than tMLI after the device has asserted DSTROBE and negated DMARQ and the host has asserted
STOP and negated
12)The device shall latch the host's CRC data from DD (15:0) on the negating edge of
13)The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA burst for any one command, at the end of the command, the device shall report the first error that occurred (see 5.5.5).
14)The device shall release DSTROBE within tIORDYZ after the host negates
15)The host shall neither negate STOP nor assert HDMARDY- until at least tACK after the host has negated
16)The host shall not assert
