Interface
At command completion (I/O registers contents to be read)
1F7H(ST) | Status information |
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1F6H(DH) | x | L | x | DV | End head No. / LBA [MSB] |
1F5H(CH) | End cylinder No. [MSB] / LBA | ||||
1F4H(CL) | End cylinder No. [LSB] / LBA | ||||
1F3H(SN) | End sector No. / LBA [LSB] | ||||
1F2 (SC) | 00(*1) |
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H |
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1F1H(ER) | Error information |
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*1 If the command is terminated due to an error, the remaining number of sectors for which data was not transferred is set in this register.
(3) READ DMA (X’C8’ or X’C9’)
This command operates similarly to the READ SECTOR(S) command except for following events.
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The data transfer starts at the timing of DMARQ signal assertion.
The device controls the assertion or negation timing of the DMARQ signal.
The device posts a status as the result of command execution only once at completion of the data transfer.
When an error, such as an unrecoverable medium error, that the command execution cannot be continued is detected, the data transfer is stopped without transferring data of sectors after the erred sector. The device generates an interrupt using the INTRQ signal and posts a status to the host system. The format of the error information is the same as the READ SECTOR(S) command.
In LBA mode
The logical block address is specified using the start head No., start cylinder No., and first sector No. fields. At command completion, the logical block address of the last sector and remaining number of sectors of which data was not transferred, like in the CHS mode, are set.
The host system can select the DMA transfer mode by using the SET FEATURES command.
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Multiword DMA transfer mode 0 to 2
Ultra DMA transfer mode 0 to 5
