Interface
Mode. The host shall not generate two rising or falling HSTROBE edges more frequently than 2 tCYC for the selected Ultra DMA mode.
3)The host shall not change the state of DD (15:0) until at least tDVH after generating an HSTROBE edge to latch the data.
4)The host shall repeat steps (1), (2) and (3) until the data transfer is complete or an Ultra DMA burst is paused, whichever occurs first.
5.5.4.3Pausing an Ultra DMA data out burst
The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.9 and 5.6.3.2 for specific timing requirements).
a)Host pausing an Ultra DMA data out burst
1)The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred.
2)The host shall pause an Ultra DMA burst by not generating an HSTROBE edge.
Note: The device shall not immediately negate DMARQ to initiate Ultra DMA burst termination when the host stops generating HSTROBE edges. If the host does not assert STOP, in order to initiate Ultra DMA burst termination, the device shall negate DDMARDY- and wait tRP before negating DMARQ.
3)The host shall resume an Ultra DMA burst by generating an HSTROBE edge.
b)Device pausing an Ultra DMA data out burst
1)The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred.
2)The device shall pause an Ultra DMA burst by negating
3)The host shall stop generating HSTROBE edges within tRFS of the device negating
4)If the device negates DDMARDY- within tSR after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero or one additional data words. If the device negates DDMARDY- greater
than tSR after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero, one or two additional data words. The
additional data words are a result of cable round trip delay and tRFS timing for the host.
5)The device shall resume an Ultra DMA burst by asserting
