Interface
[signal] | [I/O] | [Description] |
DMARQ | O | This signal is used for DMA transfer between the host system and |
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| the device. The device asserts this signal when the device |
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| completes the preparation of DMA data transfer to the host |
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| system (at reading) or from the host system (at writing). |
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| The direction of data transfer is controlled by the DIOR and |
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| DIOW signals. This signal hand shakes with the |
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| In other words, the device negates the DMARQ signal after the |
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| host system asserts the DMACK signal. When there is other data |
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| to be transferred, the device asserts the DMARQ signal again. |
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| When the DMA data transfer is performed, |
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| CS1- signals are not asserted. The DMA data transfer is a |
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| data transfer. |
+5 VDC | I | +5 VDC power supplying to the device. |
GND | - | Grounded signal at each signal wire. |
Note:
“I” indicates input signal from the host to the device.
“O” indicates output signal from the device to the host.
“I/O” indicates common output or
5.2 Logical Interface
The device can operate for command execution in either
The sector No. under the LBA mode proceeds in the ascending order with the start point of LBA0 (defined as follows).
LBA0 = [Cylinder 0, Head 0, Sector 1]
Even if the host system changes the assignment of the CHS mode by the INITIALIZE DEVICE PARAMETER command, the sector LBA address is not changed.
LBA = [((Cylinder No.) ⋅ (Number of head) + (Head No.)) ⋅ (Number of sector/track)] + (Sector No.) − 1