Fujitsu MHN2150AT, MHN2100AT Multiword data transfer, Multiword DMA data transfer timing mode

Interface

5.6.2 Multiword data transfer

Figure 5.10 shows the multiword DMA data transfer timing between the device and the host system.

			t0
DMARQ		tC	tJ
DMACK-
DIOR-/DIOW-	tI	tD	tK
Write data
DD0-DD15
		tG	tH
Read data
DD0-DD15
		tE	tF

Symbol	Timing parameter	Min.	Max.	Unit
t0	Cycle time	120	—	ns
tC	Delay time from DMACK assertion to DMARQ negation	—	35	ns
tD	Pulse width of DIOR-/DIOW-	70	—	ns
tE	Data setup time for DIOR-	—	30	ns
tF	Data hold time for DIOR-	5	—	ns
tG	Data setup time for DIOW-	20	—	ns
tH	Data hold time for DIOW-	10	—	ns
tI	DMACK setup time for DIOR-/DIOW-	0	—	ns
tJ	DMACK hold time for DIOR-/DIOW-	5	—	ns
tK	Continuous time of high level for DIOR-/DIOW-	25	—	ns

Figure 5.10 Multiword DMA data transfer timing (mode 2)

5-112 C141-E120-02EN