Fujitsu MHN2100AT, MHN2150AT Ultra DMA data out commands, Initiating an Ultra DMA data out burst

5.5 Ultra DMA Feature Set

5.5.4 Ultra DMA data out commands

5.5.4.1 Initiating an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.7 and 5.6.3.2 for specific timing requirements):

1)The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.

2)The device shall assert DMARQ to initiate an Ultra DMA burst.

3)Steps (3), (4), and (5) may occur in any order or at the same time. The host shall assert STOP.

4)The host shall assert HSTROBE.

5)The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-, DA2, DA1, and DA0 negated until after negating DMACK- at the end of the burst.

6)Steps (3), (4), and (5) shall have occurred at least tACK before the host asserts DMACK-. The host shall keep DMACK- asserted until the end of an Ultra DMA burst.

7)The device may negate DDMARDY- tZIORDY after the host has asserted DMACK-. Once the device has negated DDMARDY-, the device shall not release DDMARDY- until after the host has negated DMACK- at the end of an Ultra DMA burst.

8)The host shall negate STOP within tENV after asserting DMACK-. The host shall not assert STOP until after the first negation of HSTROBE.

9)The device shall assert DDMARDY- within tLI after the host has negated STOP. After asserting DMARQ and DDMARDY- the device shall not negate either signal until after the first negation of HSTROBE by the host.

10)The host shall drive the first word of the data transfer onto DD (15:0). This step may occur any time during Ultra DMA burst initiation.

11)To transfer the first word of data: the host shall negate HSTROBE no sooner

than tLI after the device has asserted DDMARDY-. The host shall negate HSTROBE no sooner than tDVS after the driving the first word of data onto DD (15:0).

5.5.4.2 The data out transfer

The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.8 and 5.6.3.2 for specific timing requirements):

1)The host shall drive a data word onto DD (15:0).

2)The host shall generate an HSTROBE edge to latch the new word no sooner

than tDVS after changing the state of DD (15:0). The host shall generate an HSTROBE edge no more frequently than tCYC for the selected Ultra DMA

C141-E120-02EN 5-105