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Fujitsu MPA3052AT, MPA3043AT manual Read circuit, 5 Frequency characteristic of programmable filter

Models: MPA3017AT MPA3035AT MPA3026AT MPA3052AT MPA3043AT

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4.6.3Read circuit

4.6.3Read circuit

The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the adaptive equalizer circuit. This clock signal is converted into the NRZ data by the 8/9 GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.

(1)AGC circuit

The AGC circuit automatically regulates the output amplitude to a constant value even when the input amplitude level fluctuates. The AGC amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer/inner head positions.

(2)Programmable filter

The programmable filter circuit has a low-pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost-up function that equalizes the waveform of the read signal.

Cut-off frequency of the low-pass filter and boost-up gain are controlled from each DAC circuit in read channel by an instruction of the serial data signal from MPU (M1). The MPU optimizes the cut-off frequency and boost-up gain according to the transfer frequency of each zone.

Figure 4.5 shows the frequency characteristic sample of the programmable filter.

Figure 4.5 Frequency characteristic of programmable filter

(3)Adaptive equalizer circuit

This circuit is 3-tap sampled analog transversal filter circuit that cosine-equalizes the head read signal to the partial response class 4 (PR4) waveform.

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C141-E034-02EN

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Fujitsu MPA3052AT, MPA3043AT, MPA3026AT, MPA3035AT, MPA3017AT Read circuit, 5 Frequency characteristic of programmable filter

Contents

MPA3017AT MPA3026AT MPA3035AT MPA3043AT MPA3052AT DISK DRIVES PRODUCT MANUALC141-E034-02EN Date published Revised contentsREVISION RECORD EditionChapter DEVICE CONFIGURATIONINSTALLATION CONDITIONS PREFACEConventions for Alert Messages C141-E034-02EN LIABILITY EXCEPTIONCHAPTER CONTENTSCHAPTER CHAPTERCHAPTER CHAPTERCommand descriptions Command block registersHost Commands Command code and parameters6.3.1 Power save modePower commands Data buffer configurationFIGURES Multiword DMA data transfer timing mode Protocol for command abortWRITE SECTORS command protocol Protocol for the command execution without data transferTABLES 1.1 Features 1.1.1 Functions and performance 1.1 Features 1.2 Device Specifications 1.3 Power Requirements1.4 Environmental Specifications 1.5 Acoustic Noise 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate1.1.3 Interface 1.1.2 Adaptability5 Error correction and retry by ECC 6 Write cacheC141-E034-02EN Table 1.1 Specifications 1.2 Device Specifications 1.2.1 Specifications summary1.3 Power Requirements 1.2.2 Model and product numberTable 1.2 Model names and product numbers Table 1.3 Current and power dissipation Figure 1.1 Current fluctuation Typ. at +5V when power is turned on 1.5 Acoustic Noise 1.4 Environmental SpecificationsEnvironmental specifications Table 1.5 Acoustic noise specificationTable 1.6 Shock and vibration specification 1.6 Shock and Vibration1.7 Reliability 1.9 Media Defects 1.8 Error RateFigure 2.1 Disk drive outerview CHAPTER 2 DEVICE CONFIGURATION2.1 Device Configuration 2.2 System Configuration 2.1 Device ConfigurationC141-E034-02EN 1 DiskMPA3017AT 1 disk MPA3026AT 2 disks MPA3035AT 2 disks MPA3043AT 3 disks MPA3052AT 3 disks 2 HeadFigure 2.2 Configuration of disk media heads 2.2 System Configuration 2.2.1 ATA interface Figure 2.3 1 drive system configuration2.2.2 1 drive connection HA Host adaptor AT bus Host interface Figure 2.4 2 drives configuration2.2.3 2 drives connection HostCHAPTER 3 INSTALLATION CONDITIONS 3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3.4 Jumper Settings3.1 Dimensions C141-E034-02EN Figure 3.1 DimensionsFigure 3.2 Orientation 3.2 MountingFigure 3.3 Limitation of side-mounting Figure 3.4 Mounting frame structurecabinet Table 3.1 Surface temperature measurement points and standard values Figure 3.5 Surface temperature measurement pointsMounting screw hole Service areaPower supply connector CN1 Mode Setting Pins ATA interface connector 3.3 Cable Connections 3.3.1 Device connectorFigure 3.7 Connector locations ∙ Power supply connector CN1 ∙ ATA interface connector CN1Figure 3.8 Cable connections 3.3.2 Cable connector specificationsTable 3.2 Cable connector specifications 3.3.3 Device connectionFigure 3.10 Jumper location 3.3.4 Power supply connector CN1Figure 3.9 Power supply connector pins CN1 3.4 Jumper Settings 3.4.1 Location of setting jumpers3.4.2 Factory default setting Figure 3.11 Factory default setting 3.4.3 Jumper configurationFigure 3.12 Jumper setting of master or slave device Figure 3.13 Jumper setting of Cable Select Figure 3.14 Example 1 of Cable SelectFigure 3.15 Example 2 of Cable Select Master Device 3 Special setting 1 SP1a Default mode b Special mode4.7 Servo Control 4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration4.4 Power-on sequence 4.5 Self-calibration 4.6 Read/Write circuit CHAPTER 4 THEORY OF DEVICE OPERATIONFigure 4.1 Head structure 4.2.2 Head4.2.3 Spindle 4.2.4 Actuator4.2.5 Air filter 4.3 Circuit Configuration C141-E034-02EN Figure 4.2 MPA30xxAT Block diagram4.4 Power-on Sequence Figure 4.3 Power-on operation sequence 4.5 Self-calibration 4.5.1 Self-calibration contents4.5.3 Command processing during self-calibration Table 4.1 Self-calibration execution timechartTable 4.2 Write precompensation algorithm 4.6 Read/write Circuit4.6.1 Read/write preamplifier PreAMP 4.6.2 Write circuitC141-E034-02EN Figure 4.4 Read/write circuit block diagram4.6.3 Read circuit Figure 4.5 Frequency characteristic of programmable filterC141-E034-02EN Figure 4.6 PR4 signal transfer4.6.4 Time base generator circuit 4.7 Servo Control Table 4.3 Write clock frequency and transfer rate of each zone4.7.1 Servo control circuit Figure 4.7 Block diagram of servo control circuitd. Calibration Figure 4.8 Physical sector servo configuration on disk surfacec. Seek to specified cylinder Drives the VCM to position the head to the specified cylinder4 D/A converter DAC 5 Power amplifier2 Servo burst capture circuit 3 A/D converter ADC4.7.2 Data-surface servo format 4.7.3 Servo frame formatFigure 4.9 Servo frame format 4.7.4 Actuator motor control 4.7.5 Spindle motor control 2 Acceleration mode 3 Stable rotation modeC141-E034-02EN INTERFACE 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands5.4 Command Protocol 5.5 Ultra DMA Feature Set 5.6 Timing CHAPTERFigure 5.1 Interface signals 5.1 Physical Interface 5.1.1 Interface signalsTable 5.1 Signal assignment on the interface connector 5.1.2 Signal assignment on the connectorsignal This signal is used for DMA transfer between the host system and the 5.2.1 I/O registers 5.2 Logical InterfaceI/O registers 5.2.2 Command block registers X80 Device 1 slave device Failed Diagnostic code X01 No Error Detected X02 HDC Register Compare ErrorX03 Data Buffer Compare Error X05 ROM Sum Check Error 3 Features register X1F16 Cylinder Low register X1F4 C141-E034-02EN 9 Status register X1F7DRDY CORR10 Command register X1F7 AlwaysC141-E034-02EN 5.2.3 Control block registers 5.3 Host CommandsTable 5.3 Command code and parameters 1 of 5.3.1 Command code and parametersTable 5.3 Command code and parameters 2 of Transfer sector count 5.3.2 Command descriptions1F6 HDH At command issuance I/O registers setting contents1 READ SECTORS X20 or 1F7 HCMStatus information At command completion I/O registers contents to be readError information 1F7 HSTFigure 5.2 Execution example of READ MULTIPLE command 2 Multiword DMA transfer mode ∙ The data transfer starts at the timing of DMARQ signal assertionIn LBA mode 1 Single word DMA transfer mode1F7 HST At command completion I/O registers contents to be readError information At command issuance I/O registers setting contents1F7 HST At command completion I/O registers contents to be readError information At command issuance I/O registers setting contentsStatus information At command completion I/O registers contents to be readError information 1F7 HST∙ The data transfer starts at the timing of DMARQ signal assertion At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationAt command issuance I/O registers setting contents 1 Single word DMA transfer mode2 Multiword DMA transfer mode 3 Ultra DMA transfer modeThis command can be issued in the LBA mode At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationAt command completion I/O registers contents to be read At command completion I/O registers contents to be readError information At command issuance I/O registers setting contentsError Information In LBA modeAt command issuance I/O registers setting contents At command completion I/O registers contents to be read1F7HCM At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationC141-E034-02EN Table 5.4 Information to be read by IDENTIFY DEVICE command 1 ofTable 5.4 Information to be read by IDENTIFY DEVICE command 2 of Table 5.4 Information to be read by IDENTIFY DEVICE command 3 of 14 SET FEATURES XEF At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationX‘AA’ Table 5.5 Features register values and settable modesX‘09’ Mode PIO default transfer modePIO flow control transfer mode X‘08’ Mode1F7HCM At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationTable 5.6 Diagnostic code 1 This register indicates X‘00’ in the LBA mode 17 FORMAT TRACK At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Diagnostic codeThis command is operated under the following conditions At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationAt command issuance I/O registers setting contents At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationAt command completion I/O registers contents to be read At command completion I/O registers contents to be readError information At command issuance I/O registers setting contentsPeriod of timer Point of timerDisable of timer At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read At command completion I/O registers contents to be readError information At command issuance I/O registers setting contentsError information At command issuance I/O registers setting contentsPeriod of timer At command completion I/O registers contents to be readThis command is the only way to make the device enter the sleep mode At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationThe host checks the power mode of the device with this command At command completion I/O registers contents to be readError information 27 CHECK POWER MODE X98 or XE51F7 HCM At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationFeatures Resister Table 5.7 Features Register values subcommands and functionsError information At command issuance I-O registers setting contentsSubcommand At command completion I-O registers setting contentsTable 5.8 Format of device attribute value data Format of insurance failure threshold value data ∙ Attribute ID The attribute ID is defined as follows Power-on timeNumber of power-on-power-off times Write error rate∙ Insurance failure threshold ∙ Raw attribute value Raw attributes data is retained∙ Failure prediction capability flag Bits 2 to 15 Reserved bits ∙ Check sumABRT 5.3.3 Error postingTable 5.10 Command code and parameters INDF5.4.1 Data transferring commands from device to host 5.4 Command ProtocolFigure 5.3 Read Sectors command protocol 5.4.2 Data transferring commands from host to device Figure 5.4 Protocol for command abortFigure 5.5 WRITE SECTORS command protocol Figure 5.6 Protocol for the command execution without data transfer 5.4.3 Commands without data transfer5.4.5 DMA data transfer commands 5.4.4 Other commandsFigure 5.7 Normal DMA data transfer 5.5 Ultra DMA feature set 5.5.1 Overview 5.5.2 Phases of operation 5.5.3 Ultra DMA data in commands5.5.3.1 Initiating an Ultra DMA data in burst 5.5.3.2 The data in transfer 5.5.3.3 Pausing an Ultra DMA data in burst5.5.3.4 Terminating an Ultra DMA data in burst C141-E034-02EN b Host terminating an Ultra DMA data in burst5.5.4.1 Initiating an Ultra DMA data out burst 5.5.4 Ultra DMA data out commands5.5.4.2 The data out transfer 5.5.4.3 Pausing an Ultra DMA data out burst5.5.4.4 Terminating an Ultra DMA data out burst C141-E034-02EN b Device terminating an Ultra DMA data out burst5.5.5 Ultra DMA CRC rules 5.5.6 Series termination required for Ultra DMA Table 5.11 Recommended series termination for Ultra DMAFigure 5.8 Ultra DMA termination with pull-up or pull-down C141-E034-02EN 5.6 Timing 5.6.1 PIO data transferFigure 5.9 PIO data transfer timing Figure 5.10 Single word DMA data transfer timing 5.6.2 Single word DMA data transfer5.6.3 Multiword data transfer Figure 5.11 Multiword DMA data transfer timing mode5.6.4 Ultra DMA data transfer 5.6.4.1 Initiating an Ultra DMA data in burstFigure 5.12 Initiating an Ultra DMA data in burst Table 5.12 Ultra DMA data burst timing requirements 5.6.4.2 Ultra DMA data burst timing requirementstIORDYZ tZIORDYtACK Figure 5.13 Sustained Ultra DMA data in burst 5.6.4.3 Sustained Ultra DMA data in burstFigure 5.14 Host pausing an Ultra DMA data in burst 5.6.4.4 Host pausing an Ultra DMA data in burstFigure 5.15 Device terminating an Ultra DMA data in burst 5.6.4.5 Device terminating an Ultra DMA data in burstFigure 5.16 Host terminating an Ultra DMA data in burst 5.6.4.6 Host terminating an Ultra DMA data in burstFigure 5.17 Initiating an Ultra DMA data out burst 5.6.4.7 Initiating an Ultra DMA data out burstFigure 5.18 Sustained Ultra DMA data out burst 5.6.4.8 Sustained Ultra DMA data out burstFigure 5.19 Device pausing an Ultra DMA data out burst 5.6.4.9 Device pausing an Ultra DMA data out burstFigure 5.20 Host terminating an Ultra DMA data out burst 5.6.4.10 Host terminating an Ultra DMA data out burstFigure 5.21 Device terminating an Ultra DMA data out burst 5.6.4.11 Device terminating an Ultra DMA data in burstFigure 5.22 Power-on Reset Timing 5.6.5 Power-on and resetOPERATIONS 6.1 Device Response to the Reset 6.2 Address Translation6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache 6.6 Write Cache 6.1 Device Response to the ResetFigure 6.1 Response to power-on 6.1.1 Response to power-onFigure 6.2 Response to hardware reset 6.1.2 Response to hardware reset6.1.3 Response to software reset Figure 6.3 Response to software resetMaster device Figure 6.4 Response to diagnostic command 6.1.4 Response to diagnostic command6.2.1 Default parameters Default parameters6.2 Address Translation 6.2.2 Logical address Figure 6.5 Address translation example in CHS mode6.3.1 Power save mode Figure 6.6 Address translation example in LBA mode 6.3 Power Save∙ A command other than power commands is issued 1 Active modeA device enters the active mode under the following conditions ∙ Power-on sequence is completed6.4 Defect Management 6.3.2 Power commandsDefective 6.4.1 Spare area6.4.2 Alternating defective sectors Figure 6.7 Sector slip processingFigure 6.8 Alternate cylinder assignment 6.5.1 Data buffer configuration Figure 6.9 Data buffer configuration6.5 Read-Ahead Cache 6.5.2 Caching operation 6.5.3 Usage of read segment Stores the read-requested data upto this point 4 Following shows the cache enabled data for next read commandCache enabled data HAP Segment only for read DAPEmpty data a. Sequential command just after non-sequential command3 Sequential read Mis-hit dataHit data HAP Read-ahead data DAP Last LBA Start LBA b. Sequential hitHAP Completion of transferring requested data Read-ahead dataStart LBA c. Non-sequential read command just after sequential read commandHAP Read-ahead data DAP 4 Finally, the cache data in the buffer is as follows Read-ahead dataHAP set to hit position for data transfer Last position at previous read commandDAP Last position at previous read command 3 The cache data for next read command is as follows Cache dataRequested data to be transferred DAP stopped 3 The cache data for next read command is as followsPartially hit data Lack data6.6 Write Cache When the write cache function is enabled, the transferred data from the host by the WRITE SECTORS is not completely written on the disk medium at the time that the interrupt of command complete is generated. When the unrecoverable error occurs during the write operation, the command execution is stopped. Then, when the drive receives the next command, it generates an interrupt of abnormal end. However an interrupt of abnormal end is not generated when a write automatic assignment succeeds. However, since the host may issue several write commands before the drive generates an interrupt of abnormal end, the host cannot recognize that the occurred error is for which command generally. Therefore, it is very hard to retry the unrecoverable write error for the host in the write cache operation generally. So, take care to use the write cache function Page 61-2-411-8603 Reader Comment Form FUJITSU LIMITED