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Fujitsu MPA3052AT, MPA3043AT This signal is used for DMA transfer between the host system and the

Models: MPA3017AT MPA3035AT MPA3026AT MPA3052AT MPA3043AT

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[signal]	[I/O]	[Description]
IORDY,	O	This signal is negated to extend the host transfer cycle of any host
DDMARDY–,		register access (Read or Write) when the device is not ready to
DSTROBE		respond to a data transfer request.
		DDMARDY– is a flow control signal for Ultra DMA data out bursts.
		This signal is asserted by the device to indicate to the host that the
		device is ready to receive Ultra DMA data out bursts. The device
		may negate DDMARDY– to pause an Ultra DMA data out burst.
		DSTROBE is the data in strobe signal from the device for an Ultra
		DMA data in burst. Both the rising and falling edge of DSTROBE
		latch the data from DATA 0-15 into the host. The device may stop
		generating DSTROBE edges to pause an Ultra DMA data in burst.
CSEL	I	This signal to configure the device as a master or a slave device.
		When CSEL signal is grounded, the IDD is a master device.
		When CSEL signal is open, the IDD is a slave device.
		This signal is pulled up with 240 kΩ resistor.
DMACK–	I	The host system asserts this signal as a response that the host system
		receive data or to indicate that data is valid.
DMARQ	O	This signal is used for DMA transfer between the host system and the
		device. The device asserts this signal when the device completes the
		preparation of DMA data transfer to the host system (at reading) or
		from the host system (at writing).
		The direction of data transfer is controlled by the IOR- and IOW-
		signals. In other word, the device negates the DMARQ signal after
		the host system asserts the DMACK– signal. When there is another
		data to be transferred, the device asserts the DMARQ signal again.
		When the DMA data transfer is performed, IOCW16–, CS0– and
		CS1- signals are not asserted. The DMA data transfer is a 16-bit data
		transfer.
GND	–	Grounded

Note:

"I" indicates input signal from the host to the device. "O" indicates output signal from the device to the host.

"I/O" indicates common output or bi-directional signal between the host and the device.

C141-E034-02EN

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Fujitsu MPA3052AT, MPA3043AT, MPA3026AT, MPA3035AT manual This signal is used for DMA transfer between the host system and the

Contents

MPA3017AT MPA3026AT MPA3035AT MPA3043AT MPA3052AT DISK DRIVES PRODUCT MANUALC141-E034-02EN Edition Revised contentsREVISION RECORD Date publishedPREFACE DEVICE CONFIGURATIONINSTALLATION CONDITIONS ChapterConventions for Alert Messages LIABILITY EXCEPTION C141-E034-02ENCHAPTER CONTENTSCHAPTER CHAPTERCHAPTER CHAPTERCommand code and parameters Command block registersHost Commands Command descriptionsData buffer configuration Power save modePower commands 6.3.1FIGURES Protocol for the command execution without data transfer Protocol for command abortWRITE SECTORS command protocol Host pausing an Ultra DMA data in burstTABLES 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate 1.1 Features 1.2 Device Specifications 1.3 Power Requirements1.4 Environmental Specifications 1.5 Acoustic Noise 1.1 Features 1.1.1 Functions and performance1.1.2 Adaptability 1.1.3 Interface5 Error correction and retry by ECC 6 Write cacheC141-E034-02EN 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 Specifications1.3 Power Requirements 1.2.2 Model and product numberTable 1.2 Model names and product numbers Table 1.3 Current and power dissipation Figure 1.1 Current fluctuation Typ. at +5V when power is turned on Table 1.5 Acoustic noise specification 1.4 Environmental SpecificationsEnvironmental specifications 1.5 Acoustic NoiseTable 1.6 Shock and vibration specification 1.6 Shock and Vibration1.7 Reliability 1.8 Error Rate 1.9 Media Defects2.1 Device Configuration CHAPTER 2 DEVICE CONFIGURATION2.1 Device Configuration 2.2 System Configuration Figure 2.1 Disk drive outerviewMPA3043AT 3 disks MPA3052AT 3 disks 2 Head 1 DiskMPA3017AT 1 disk MPA3026AT 2 disks MPA3035AT 2 disks C141-E034-02ENFigure 2.2 Configuration of disk media heads 2.2 System Configuration 2.2.1 ATA interface Figure 2.3 1 drive system configuration2.2.2 1 drive connection Host Figure 2.4 2 drives configuration2.2.3 2 drives connection HA Host adaptor AT bus Host interfaceCHAPTER 3 INSTALLATION CONDITIONS 3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3.4 Jumper Settings3.1 Dimensions Figure 3.1 Dimensions C141-E034-02EN3.2 Mounting Figure 3.2 OrientationFigure 3.3 Limitation of side-mounting Figure 3.4 Mounting frame structurecabinet Figure 3.5 Surface temperature measurement points Table 3.1 Surface temperature measurement points and standard valuesService area Mounting screw hole∙ Power supply connector CN1 ∙ ATA interface connector CN1 3.3 Cable Connections 3.3.1 Device connectorFigure 3.7 Connector locations Power supply connector CN1 Mode Setting Pins ATA interface connector3.3.3 Device connection 3.3.2 Cable connector specificationsTable 3.2 Cable connector specifications Figure 3.8 Cable connections3.4.1 Location of setting jumpers 3.3.4 Power supply connector CN1Figure 3.9 Power supply connector pins CN1 3.4 Jumper Settings Figure 3.10 Jumper location3.4.2 Factory default setting Figure 3.11 Factory default setting 3.4.3 Jumper configurationFigure 3.12 Jumper setting of master or slave device Figure 3.13 Jumper setting of Cable Select Figure 3.14 Example 1 of Cable SelectFigure 3.15 Example 2 of Cable Select Master Device 3 Special setting 1 SP1a Default mode Slave DeviceCHAPTER 4 THEORY OF DEVICE OPERATION 4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration4.4 Power-on sequence 4.5 Self-calibration 4.6 Read/Write circuit 4.7 Servo Control4.2.2 Head Figure 4.1 Head structure4.2.3 Spindle 4.2.4 Actuator4.2.5 Air filter 4.3 Circuit Configuration Figure 4.2 MPA30xxAT Block diagram C141-E034-02EN4.4 Power-on Sequence Figure 4.3 Power-on operation sequence 4.5.1 Self-calibration contents 4.5 Self-calibrationTable 4.1 Self-calibration execution timechart 4.5.3 Command processing during self-calibration4.6.2 Write circuit 4.6 Read/write Circuit4.6.1 Read/write preamplifier PreAMP Table 4.2 Write precompensation algorithmFigure 4.4 Read/write circuit block diagram C141-E034-02ENFigure 4.5 Frequency characteristic of programmable filter 4.6.3 Read circuitFigure 4.6 PR4 signal transfer C141-E034-02EN4.6.4 Time base generator circuit Table 4.3 Write clock frequency and transfer rate of each zone 4.7 Servo ControlFigure 4.7 Block diagram of servo control circuit 4.7.1 Servo control circuitDrives the VCM to position the head to the specified cylinder Figure 4.8 Physical sector servo configuration on disk surfacec. Seek to specified cylinder d. Calibration3 A/D converter ADC 5 Power amplifier2 Servo burst capture circuit 4 D/A converter DAC4.7.2 Data-surface servo format 4.7.3 Servo frame formatFigure 4.9 Servo frame format 4.7.4 Actuator motor control 4.7.5 Spindle motor control 2 Acceleration mode 3 Stable rotation modeC141-E034-02EN CHAPTER 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands5.4 Command Protocol 5.5 Ultra DMA Feature Set 5.6 Timing INTERFACE5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 Interface signals5.1.2 Signal assignment on the connector Table 5.1 Signal assignment on the interface connectorsignal This signal is used for DMA transfer between the host system and the 5.2 Logical Interface 5.2.1 I/O registersI/O registers 5.2.2 Command block registers 3 Features register X1F1 Diagnostic code X01 No Error Detected X02 HDC Register Compare ErrorX03 Data Buffer Compare Error X05 ROM Sum Check Error X80 Device 1 slave device Failed6 Cylinder Low register X1F4 CORR 9 Status register X1F7DRDY C141-E034-02EN10 Command register X1F7 AlwaysC141-E034-02EN 5.3 Host Commands 5.2.3 Control block registers5.3.1 Command code and parameters Table 5.3 Command code and parameters 1 ofTable 5.3 Command code and parameters 2 of 5.3.2 Command descriptions Transfer sector count1F7 HCM At command issuance I/O registers setting contents1 READ SECTORS X20 or 1F6 HDH1F7 HST At command completion I/O registers contents to be readError information Status informationFigure 5.2 Execution example of READ MULTIPLE command 3 READ DMA XC8 or XC9 ∙ The data transfer starts at the timing of DMARQ signal assertionAt command issuance I/O registers setting contents In LBA modeAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information 1F7 HSTAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information 1F7 HST1F7 HST At command completion I/O registers contents to be readError information Status informationError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read ∙ The data transfer starts at the timing of DMARQ signal assertionError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 1 Single word DMA transfer modeError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read This command can be issued in the LBA modeAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information At command completion I/O registers contents to be readError Information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 11 INITIALIZE DEVICE PARAMETERSError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 1F7HCMTable 5.4 Information to be read by IDENTIFY DEVICE command 1 of C141-E034-02ENTable 5.4 Information to be read by IDENTIFY DEVICE command 2 of Table 5.4 Information to be read by IDENTIFY DEVICE command 3 of Error information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 14 SET FEATURES XEFTable 5.5 Features register values and settable modes X‘AA’X‘00’ PIO default transfer mode00000 PIO flow control transfer modeError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 1F7HCMTable 5.6 Diagnostic code Diagnostic code At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read The READ LONG command supports only single sector operationError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read This command is operated under the following conditionsError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information At command completion I/O registers contents to be readAt command issuance I/O registers setting contents Point of timerDisable of timer Period of timerAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information At command completion I/O registers contents to be readAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsPeriod of timer Error informationError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read This command is the only way to make the device enter the sleep mode27 CHECK POWER MODE X98 or XE5 At command completion I/O registers contents to be readError information The host checks the power mode of the device with this commandError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 1F7 HCMTable 5.7 Features Register values subcommands and functions Features ResisterAt command completion I-O registers setting contents At command issuance I-O registers setting contentsSubcommand Error informationTable 5.8 Format of device attribute value data Format of insurance failure threshold value data Write error rate Power-on timeNumber of power-on-power-off times ∙ Attribute ID The attribute ID is defined as followsBits 2 to 15 Reserved bits ∙ Check sum ∙ Raw attribute value Raw attributes data is retained∙ Failure prediction capability flag ∙ Insurance failure thresholdINDF 5.3.3 Error postingTable 5.10 Command code and parameters ABRT5.4 Command Protocol 5.4.1 Data transferring commands from device to hostFigure 5.3 Read Sectors command protocol Figure 5.4 Protocol for command abort 5.4.2 Data transferring commands from host to deviceFigure 5.5 WRITE SECTORS command protocol 5.4.3 Commands without data transfer Figure 5.6 Protocol for the command execution without data transfer5.4.4 Other commands 5.4.5 DMA data transfer commandsFigure 5.7 Normal DMA data transfer 5.5 Ultra DMA feature set 5.5.1 Overview 5.5.2 Phases of operation 5.5.3 Ultra DMA data in commands5.5.3.1 Initiating an Ultra DMA data in burst 5.5.3.3 Pausing an Ultra DMA data in burst 5.5.3.2 The data in transfer5.5.3.4 Terminating an Ultra DMA data in burst b Host terminating an Ultra DMA data in burst C141-E034-02EN5.5.4 Ultra DMA data out commands 5.5.4.1 Initiating an Ultra DMA data out burst5.5.4.3 Pausing an Ultra DMA data out burst 5.5.4.2 The data out transfer5.5.4.4 Terminating an Ultra DMA data out burst b Device terminating an Ultra DMA data out burst C141-E034-02EN5.5.5 Ultra DMA CRC rules 5.5.6 Series termination required for Ultra DMA Table 5.11 Recommended series termination for Ultra DMAFigure 5.8 Ultra DMA termination with pull-up or pull-down 5.6 Timing 5.6.1 PIO data transfer C141-E034-02ENFigure 5.9 PIO data transfer timing 5.6.2 Single word DMA data transfer Figure 5.10 Single word DMA data transfer timing5.6.3 Multiword data transfer Figure 5.11 Multiword DMA data transfer timing mode5.6.4 Ultra DMA data transfer 5.6.4.1 Initiating an Ultra DMA data in burstFigure 5.12 Initiating an Ultra DMA data in burst 5.6.4.2 Ultra DMA data burst timing requirements Table 5.12 Ultra DMA data burst timing requirementstIORDYZ tZIORDYtACK 5.6.4.3 Sustained Ultra DMA data in burst Figure 5.13 Sustained Ultra DMA data in burst5.6.4.4 Host pausing an Ultra DMA data in burst Figure 5.14 Host pausing an Ultra DMA data in burst5.6.4.5 Device terminating an Ultra DMA data in burst Figure 5.15 Device terminating an Ultra DMA data in burst5.6.4.6 Host terminating an Ultra DMA data in burst Figure 5.16 Host terminating an Ultra DMA data in burst5.6.4.7 Initiating an Ultra DMA data out burst Figure 5.17 Initiating an Ultra DMA data out burst5.6.4.8 Sustained Ultra DMA data out burst Figure 5.18 Sustained Ultra DMA data out burst5.6.4.9 Device pausing an Ultra DMA data out burst Figure 5.19 Device pausing an Ultra DMA data out burst5.6.4.10 Host terminating an Ultra DMA data out burst Figure 5.20 Host terminating an Ultra DMA data out burst5.6.4.11 Device terminating an Ultra DMA data in burst Figure 5.21 Device terminating an Ultra DMA data out burst5.6.5 Power-on and reset Figure 5.22 Power-on Reset Timing6.6 Write Cache 6.1 Device Response to the Reset 6.1 Device Response to the Reset 6.2 Address Translation6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache OPERATIONS6.1.1 Response to power-on Figure 6.1 Response to power-on6.1.2 Response to hardware reset Figure 6.2 Response to hardware reset6.1.3 Response to software reset Figure 6.3 Response to software resetMaster device 6.1.4 Response to diagnostic command Figure 6.4 Response to diagnostic command6.2.1 Default parameters Default parameters6.2 Address Translation 6.2.2 Logical address Figure 6.5 Address translation example in CHS modeFigure 6.6 Address translation example in LBA mode 6.3 Power Save 6.3.1 Power save mode∙ Reset hardware or software 2 Idle mode ∙ Power-on sequence is completed∙ A command other than power commands is issued ∙ After completion of power-on sequence6.3.2 Power commands 6.4 Defect ManagementFigure 6.7 Sector slip processing 6.4.1 Spare area6.4.2 Alternating defective sectors DefectiveFigure 6.8 Alternate cylinder assignment 6.5.1 Data buffer configuration Figure 6.9 Data buffer configuration6.5 Read-Ahead Cache 6.5.2 Caching operation 6.5.3 Usage of read segment HAP Segment only for read DAP 4 Following shows the cache enabled data for next read commandCache enabled data Stores the read-requested data upto this pointMis-hit data a. Sequential command just after non-sequential command3 Sequential read Empty dataRead-ahead data HAP Read-ahead data DAP Last LBA Start LBA b. Sequential hitHAP Completion of transferring requested data Hit data4 Finally, the cache data in the buffer is as follows Read-ahead data c. Non-sequential read command just after sequential read commandHAP Read-ahead data DAP Start LBA3 The cache data for next read command is as follows Cache data Last position at previous read commandDAP Last position at previous read command HAP set to hit position for data transferLack data DAP stopped 3 The cache data for next read command is as followsPartially hit data Requested data to be transferred6.6 Write Cache When the write cache function is enabled, the transferred data from the host by the WRITE SECTORS is not completely written on the disk medium at the time that the interrupt of command complete is generated. When the unrecoverable error occurs during the write operation, the command execution is stopped. Then, when the drive receives the next command, it generates an interrupt of abnormal end. However an interrupt of abnormal end is not generated when a write automatic assignment succeeds. However, since the host may issue several write commands before the drive generates an interrupt of abnormal end, the host cannot recognize that the occurred error is for which command generally. Therefore, it is very hard to retry the unrecoverable write error for the host in the write cache operation generally. So, take care to use the write cache function Page 61-2-411-8603 FUJITSU LIMITED Reader Comment Form